The CPS-8, device number IDT80KSW0003, is a serial RapidIO (sRIO) switch
whose functionality is central to routing packets for distribution among DSPs,
processors, FPGAs, other switches, or any other sRIO-based devices. It may
also be used in serial RapidIO backplane switching. The CPS-8 supports serial
RapidIO packet switching (unicast, multicast, and an optional broadcast) from
any of its 8 input ports to any of its 8 output ports.
u
Datasheet
80KSW0003
2 Features
u
Performance
–
20 Gbps of peak switching bandwidth
–
Non-blocking data flow architecture within each sRIO priority
–
Very low latency for all packet length and load condition
–
Internal queuing buffer and retransmit buffer
–
Standard receiver based physical layer flow control
u
Features
–
Configurable for Cut Through or Store And Forward data flow
–
Device configurable through any of sRIO ports, I
2
C, or JTAG
–
Packet Trace. Each port provides the ability to match the first 160 bits
–
–
–
–
–
–
–
–
–
–
–
–
–
Interfaces - sRIO
–
8 bidirectional serial RapidIO (sRIO) lanes v 1.3
–
Port Speeds selectable: 3.125Gbps, 2.5Gbps, or 1.25Gbps
–
All lanes support short haul or long haul reach for each PHY speed
–
Configurable port count to up to eight 1x ports, two 4x ports, or 4 1x
–
Lanes can be configured as individual non-redundant 1x ports, as part
and 1 4x ports
of a redundant 1x port, or as part of a 4x port
–
Support for two separate port rates for each quad
–
Supports standard 4 levels of priority
–
Error management support
u
Interfaces - I
2
C
–
Provides I
2
C port for maintenance and error reporting
–
Master or Slave Operation
–
Master allows power-on configuration from external ROM
–
Master mode configuration with external image compressing and
checksum
of any packet against up to 4 programmable comparison values to
copy the packet to a programmable output trace port
Packet Filter. Each port also provides the ability to filter the packet
based on comparisons against these same 4 programmable values
mentioned above
Supports up to 10 simultaneous multicast masks
Broadcast support
Port Loopback Debug Feature
Software assisted error recovery, supporting hot swap
Ports may be individually turned off to reduce power
PMON counters for monitor and diagnostics. Per input port and
output port counters
SerDes physical diagnostic registers
Embedded PRBS generation and detection with programmable poly-
nomials support Bit Error Rate (BER) testing
0.13um technology
Low power dissipation
Full JTAG Boundary Scan Support (IEEE1149.1 & 1149.6)
Package: 324-ball grid array, 19mm x 19mm, 1.0mm ball pitch
3 Block Diagram
Ln0
Ln1
Ln2
Ln3
S e r ia l R a p id I O S w it c h
s R IO
E n h a n c e d
Q u a d
(u p to 4 p o rts )
s R IO
E n h a n c e d
Q u a d
(u p to 4 p o rts )
Ln4
Ln5
Ln6
Ln7
M a in te n a n c e
&
E rro r
M a n a g e m e n t
J T A G
C o n fig u ra tio n
I
2
C
Figure 1 Block diagram
1 of 47
March 31, 2008
DSC 5697
IDT80KSW0003
Datasheet
4 Device Description
The CPS-8 is optimized for DSP cluster applications at board level. Its main function is to have a backplane interface which can connect to a back-
plane switch or directly to multiple RF cards. On the line card side it can also connect to multiple ports. It supports up to 8 ports which are configurable
as line card, or backplane ports. It is an end-point free (switch) device in an sRIO network.
The CPS-8 receives packets from up to 8 ports. The CPS offers full support for normal switching as well as enhanced functions:
1) Normal Switching:
All packets are switched in accordance with standard serial RapidIO specifications, with packet destination IDs determining
how the packet is routed.
Three major options exist within this category:
a.
Multicast: If a Multicast ID is received, the CPS-8 performs a multicast as defined in the sRIO multicast registers.
b. Unicast: All other operations are performed as specified in sRIO.
c. Maintenance packets: As specified by sRIO.
The sRIO Switch supports a peak throughput of 20 Gbps which is the line rate for 8 ports in 1x configuration, each at 2.5 Gbps (3.125 Gbps minus the
sRIO-defined 8b10b encoding), and switches dynamically in accordance with the packet headers and priorities.
2) Enhanced functions
Enhanced features are provided for support of system debug. These features which are optional for the user consist of two major functions:
a. Packet Trace: The Packet Trace feature provides at-speed checking of the first 160 bits (header plus a portion of any payload) of every incom-
ing packet against user-defined comparison register values. The trace feature is available on all serial RapidIO ports, each acting indepen-
dently from one another. If the trace feature is enabled for a given port, every incoming packet is checked for a match against up to four
comparison registers. In the event of a match, either of two possible user defined actions may take place:
i) not only does the packet route normally through the switch to its appropriate destination port, but this same packet is replicated and sent to
a “trace port.” The trace port itself may be any of the standard serial RapidIO ports. The port used for the trace port is defined by the user
through simple register configuration.
ii) the packet is dropped.
If there is no match, the packets route normally through the switch with no action taken.
The Packet Trace feature can be used during system bring-up and prototyping to identify particular packet types of interest to the user. It might
be used in security applications, where packets must be checked for either correct or incorrect tags in either of the header or payload. Identi-
fied (match) packets are then routed to the trace port for receipt by a host processor, which can perform an intervention at the software level.
b. Port Loopback: The CPS-8 offers internal loopback for each port that may be used for system debug of the high speed sRIO ports. By
enabling loopback on a given port, packets sent to the port’s receiver are immediately looped back at the physical layer to the transmitter -
bypassing the higher logical or transport layers.
c. Broadcast: Each multicast mask can be configured so that the source port is included among the destination ports for that multicast operation.
The CPS-8 can be programmed through any one or combination of sRIO, I
2
C, or JTAG. Note that any sRIO port may be used for programming. The
CPS-8 can also configure itself on power-up by reading directly from ROM over I
2
C in master mode.
2 of 47
March 31, 2008
IDT80KSW0003
Datasheet
5 Applications
Central switch based wireless processing
CPU
T o /F ro m
TD M based
80KSW 0003
W A N /P u b lic
T o /F ro m
IP b a s e d
S e r ia l R a p id IO
DSP
DSP
Figure 2 Application Overview
Note: The CPS-8 provides direct support for backplane connections using the serial RapidIO standard. The addition of an appropriate bridge (e.g.,
CPRI
sRIO)
allows for further backplane flexibility, accommodating designs based on a wide range of standards such as CPRI, OBSAI, GbE or
PCIe.
In a macro wireless station, a switch-based raw data combination and distribution architecture is widely adopted. Switch based architecture provides
high flexibility and high resource efficiency. The raw data from the Radio Unit is distributed to one or more processing cards by unicast or multicast.
Aggregating raw data from processing cards to a bufferless chain can be done by a fast non-blocking switch.
Media Gateway and general processing
Note: The CPS-8 provides direct support for backplane connections using the serial RapidIO standard.
Though SAR and RTP is usually processed by NP/Processor, DSP is more efficient for TDM conversion and compression. A low jitter switch enables
the full utilization of DSP processing power. Priority support, fast switching, and multicasting will differentiate class of traffic to provide QoS.
6 Functional Overview
IDT’s CPS-8 is optimized for either board-level DSP/ASIC cluster applications or module-level distributed processing application. Up to 8 serial
RapidIO ports fully meet the standard V1.3 specification. The physical lanes may be configured to work at 3.125, 2.5, or 1.25 Gbps and in short haul
or long haul.
The CPS-8 switch has a sustained 20Gbps bandwidth. Also three major options exist within this category:
a. Multicast: If a Multicast ID is received, the CPS-8 performs a multicast as defined by the device’s configurable sRIO multicast
mask registers. Also optional for broadcast.
b. Unicast: All other operations are performed as specified in sRIO.
c. Maintenance packets: As specified in sRIO.
The CPS-8 supports a “Store and Forward” and an optional “Cut Through” packet forward methodology. Refer to “CPS-8 User Manual” for details.
The CPS-8 can be programmed through a CPU or a DSP connected to one of the sRIO ports of the device or with a CPU connected to an I
2
C or JTAG
bus. It can also work along with a I
2
C configuration memory. This option is added to allow the CPS-8 to work in “remote stand alone” mode.
3 of 47
March 31, 2008
IDT80KSW0003
Datasheet
Each sRIO port provides a packet trace capability. For any packet received by a port, a comparison between the first 160 bits and up to four configu-
rable values can be performed. A match against any of these parameters will result in a copy of the packet and a route of the packet to a configurable
ouput port. This feature can be used as a tactical function to track user data or in a debug environment to test how specific packets are moving
through the platform.
Each sRIO port also provides a packet filter capability. For any packet received by a port, a comparison between the first 160 bits and up to the same
four configurable values mentioned above can be performed. A match against any of these parameters will result in the packet being filtered.
7 Interface Overview
Rext
8 Differential sRIO Lanes
1.25, 2.5, or 3.125 Gbps
JTAG Interface
IDT CPS-8
RST
REF_CLK
I2C Interface
400KHz
SPD[1:0]
IRQ
Figure 3 Diagram of the CPS-8 Interfaces
sRIO Ports
The sRIO interfaces are the main communication ports on the chip. These ports are compliant with the serial RapidIO v. 1.3 specifications. Please
refer to the serial RapidIO specifications for full detail [2-10].
The device provides 8 differential dual simplex transceivers dedicated to sRIO I/O. These can be independently configured to run in various configura-
tions as 1x- or 4x-ports. The CPS-8 supports a maximum of 2 times 4x-ports, or 8 times 1x-ports, as well as 4 1x and 1 4x ports.
The device has a proprietary implementation which we refer to as an “Enhanced Quad.” An Enhanced Quad can be operated in standard sRIO mode
like the standard quads. Additionally the Enhanced Quad can be register-configured to run as 4 independent 1x-ports - any of which can be enabled at
a given time. In this manner, the user has the flexibility to use one, multiple, or all four lanes in 1x-mode. For example, lanes 0 - 3 are programmable
into one 4x- or four 1x-ports. This is unlike the standard sRIO port implementation that, when configured as a 1x-port, renders the remaining 3 possible
connections unused.
The device control of each of lane parameters (data rate, transmitter pre-emphasis, drive strength) can be separately configured, such that the char-
acteristics for lanes 0 and 1 can be different from those for lanes 2 and 3 in one quad. The ability to control reset and initialization of lanes 0 and 1
versus lanes 2 and 3 separately is also provided. So each 2 lanes (lanes 0, 1 and lanes 3,4) at the granularity of the half quad can be programmed to
run independently at 1.25, 2.5, or 3.125Gbps and handle long or short haul serial transmission per RIO serial specification.
4 of 47
March 31, 2008
IDT80KSW0003
Datasheet
I
2
C Bus
This interface may be used as an alternative to the standard sRIO or JTAG ports to program the chip and to check the status of registers - including
the error reporting registers. It is fully compliant with the I
2
C specification, it supports master mode and slave mode, also supports both Fast-mode and
Standard-mode buses [1]. Refer to the “I
2
C” section for full detail.
JTAG TAP Port
This TAP interface is IEEE1149.1 (JTAG) and 1149.6 (AC Extest) compliant [10, 11]. It may also be used as an alternative to the standard sRIO or I
2
C
ports to program the chip and to check the status of registers - including the error reporting registers. It has 5 pins. Refer to the JTAG chapter for full
detail.
Interrupt (IRQ)
An interrupt output is provided in support of Error Management functionality. This output may be used to flag a host processor in the event of error
conditions within the device. Refer to the Error Handling chapter for full detail.
Reset
A single Reset pin is used for full reset of the CPS-8, including setting all registers to power-up defaults. Refer to the Reset & Initialization chapter for
full detail.
Clock
The single system clock (REF_CLK+ / -) is a 156.25MHz differential clock.
Rext (Rextn & Rextp)
These pins are used to establish the drive bias on the SerDes output. An external bias resistor is required. The two pins must be connected to one
another with a 12k Ohm resistor. This provides CML driver stability across process and temperature.
SPD[1:0]
Speed Select Pins. These pins define the sRIO port speed at RESET for all ports. The RESET setting may be overridden by subsequent programming
of the QUAD_CTRL register. SPD[1:0] = {00 = 1.25G, 01 = 2.5G, 10 = 3.125G, 11 = RESERVED}. These pins must remain STATICALLY BIASED
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
