FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ICS844003BI-01
Features
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Three differential LVDS output pairs on two banks, Bank A with
one LVDS pair and Bank B with two LVDS output pairs
Using a 19.53125MHz or 25MHz crystal, the two output banks
can be independently set for 625MHz, 312.5MHz, 156.25MHz
or 125MHz
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
VCO range: 490MHz - 680MHz
RMS phase jitter @ 156.25MHz (1.875MHz – 20MHz):
0.56ps (typical)
Full 3.3V supply mode
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
General Description
The ICS844003BI-01 is a 3 differential output LVDS
Synthesizer designed to generate Ethernet refer-
HiPerClockS™
ence clock frequencies and is a member of the
HiPerClocks™ family of high performance clock
solutions from IDT. Using a 19.53125MHz or
25MHz, 18pF parallel resonant crystal, the following frequencies
can be generated based on the settings of 4 frequency select pins
(DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz, 312.5MHz,
156.25MHz, and 125MHz. The 844003BI-01 has 2 output banks,
Bank A with 1 differential LVDS output pair and Bank B with 2
differential LVDS output pairs.
ICS
The two banks have their own dedicated frequency select pins and
can be independently set for the frequencies mentioned above.
The ICS844003BI-01 uses IDT’s 3
rd
generation low phase noise
VCO technology and can achieve 1ps or lower typical rms phase
jitter, easily meeting Ethernet jitter requirements. The
ICS844003BI-01 is packaged in a small 24-pin TSSOP package.
Pin Assignment
DIV_SELB0
VCO_SEL
MR
V
DDO_A
QA0
nQA0
OEB
OEA
FB_DIV
V
DDA
V
DD
DIV_SELA0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIV_SELB1
V
DDO_B
QB0
nQB0
QB1
nQB1
XTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
GND
DIV_SELA1
Block Diagram
OEA
Pullup
DIV_SELA[1:0]
Pullup
VCO_SEL
Pullup
Pulldown
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.925mm
package body
G Package
QA0
0
00
01
10
11
÷1
÷2
÷3
÷4
(default)
QA0
REF_CLK
0
XTAL_IN
OSC
XTAL_OUT
XTAL_SEL
Pullup
1
Phase
Detector
VCO
1
QB0
FB_DIV
0 = ÷25 (default)
1 = ÷32
00
01
10
11
÷2
÷4
÷5
÷8
(default)
QB0
QB1
QB1
FB_DIV
Pulldown
DIV_SELB[1:0]
Pullup
MR
Pulldown
OEB
Pullup
IDT™ / ICS™
LVDS FREQUENCY SYNTHESIZER
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ICS844003BGI-01 REV. A AUGUST 21, 2008
ICS844003BI-01
FEMTOCLOCKS™CRYSTAL-TO- LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1,
24
Name
DIV_SELB0,
DIV_SELB1
Input
Type
Pullup
Description
Division select pin for Bank B. Default = HIGH.
LVCMOS/LVTTL interface levels. See Table 3B.
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an
internal pulldown resistor so the power-up default state of outputs and dividers
are enabled. LVCMOS/LVTTL interface levels.
Output supply pin for Bank A outputs.
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH, the
output pairs on Bank B are enabled. When logic LOW, the output pairs are in a
high impedance state. Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3E.
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair in Bank A is enabled. When logic LOW, the output pair is in a high
impedance state. Has an internal pullup resistor so the default power-up state of
output is enabled. LVCMOS/LVTTL interface levels. See Table 3D.
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. See Table 3C.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Pullup
Division select pin for Bank A. Default = HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit
with a single-ended reference clock.
Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to
low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
Crystal select pin. Selects between the single-ended REF_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pin for Bank B outputs.
2
VCO_SEL
Input
Pullup
3
MR
Input
Pulldown
4
5, 6
V
DDO_A
QA0, nQA0
Power
Output
7
OEB
Input
Pullup
8
OEA
Input
Pullup
9
10
11
12,
13
14
15,
16
FB_DIV
V
DDA
V
DD
DIV_SELA0,
DIV_SELA1
GND
XTAL_OUT,
XTAL_IN
Input
Power
Power
Input
Power
Input
Pulldown
17
REF_CLK
Input
18
19, 20
21, 22
23
XTAL_SEL
nQB1, QB1
nQB0, QB0
V
DDO_B
Input
Output
Output
Power
Pullup
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
IDT™ / ICS™
LVDS FREQUENCY SYNTHESIZER
2
ICS844003BGI-01 REV. A AUGUST 21, 2008
ICS844003BI-01
FEMTOCLOCKS™CRYSTAL-TO- LVDS FREQUENCY SYNTHESIZER
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
Ω
k
Ω
Function Tables
Table 3A. Output Bank A Configuration
Select Function Table
Inputs
DIV_SELA1
0
0
1
1
DIV_SELA0
0
1
0
1
Outputs
QA0/ nQA0
÷1
÷2
÷3
÷4 (default)
Table 3B. Output Bank B Configuration
Select Function Table
Inputs
DIV_SELB1
0
0
1
1
DIV_SELB0
0
1
0
1
Outputs
QB[0:1]/ nQB[0:1]
÷2
÷4
÷5
÷8 (default)
Table 3C. Feedback Divider Configuration
Select Function Table
Input
FB_DIV
0
1
Feedback Divide
÷25 (default)
÷32
Table 3D. OEA Select Function Table
Input
OEA
0
1
Outputs
QA0/ nQA0
High Impedance
Active (default)
Table 3E. OEB Select Function Table
Input
OEB
0
1
Outputs
QB[0:1]/ nQB[0:1]
High Impedance
Active (default)
IDT™ / ICS™
LVDS FREQUENCY SYNTHESIZER
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ICS844003BGI-01 REV. A AUGUST 21, 2008
ICS844003BI-01
FEMTOCLOCKS™CRYSTAL-TO- LVDS FREQUENCY SYNTHESIZER
Table 3F. Bank A Frequency Table
Inputs
Crystal Frequency
(MHz)
25
25
20
22.5
25
24
20
19.44
19.44
15.625
18.75
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
1
1
1
1
1
1
1
DIV_SELA1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
DIV_SELA0
0
1
1
0
1
1
1
0
1
1
0
1
1
1
Feedback
Divider
Bank A
Output Divider
M/N
Multiplication
Factor
25
12.5
12.500
8.333
6.25
6.25
6.25
32
16
16
10.667
8
8
8
QA0/ nQA0
Output Frequency
(MHz)
625
312.5
250
187.5
156.25
150
125
622.08
311.04
250
200
155.52
150
125
25
25
25
25
25
25
25
32
32
32
32
32
32
32
1
2
2
3
4
4
4
1
2
2
3
4
4
4
IDT™ / ICS™
LVDS FREQUENCY SYNTHESIZER
4
ICS844003BGI-01 REV. A AUGUST 21, 2008
ICS844003BI-01
FEMTOCLOCKS™CRYSTAL-TO- LVDS FREQUENCY SYNTHESIZER
Table 3G. Bank B Frequency Table
Inputs
Crystal Frequency
(MHz)
25
20
25
24
20
25
25
24
20
19.44
15.625
19.44
18.75
15.625
15.625
19.44
18.75
15.625
FB_DIV
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
DIV_SELB1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
DIV_SELB0
0
0
1
1
1
0
1
1
1
0
0
1
1
1
0
1
1
1
Feedback
Divider
Bank B
Output Divider
M/N
Multiplication
Factor
12.5
12.5
6.25
6.25
6.25
5
3.125
3.125
3.125
16
16
8
8
8
6.4
4
4
4
QBx/ nQBx
Output Frequency
(MHz)
312.5
250
156.25
150
125
125
78.125
75
62.5
311.04
250
155.52
150
125
100
77.76
75
62.5
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
2
2
4
4
4
5
8
8
8
2
2
4
4
4
5
8
8
8
IDT™ / ICS™
LVDS FREQUENCY SYNTHESIZER
5
ICS844003BGI-01 REV. A AUGUST 21, 2008
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