74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
Rev. 3 — 30 August 2012
Product data sheet
1. General description
The 74HC132; 74HCT132 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7A
The 74HC132; 74HCT132 is a quad 2-input NAND gate with Schmitt trigger inputs. This
device features reduced input threshold levels to allow interfacing to TTL logic levels.
Inputs also include clamp diodes that enable the use of current limiting resistors to
interface inputs to voltages in excess of V
CC
. Schmitt trigger inputs transform slowly
changing input signals into sharply defined jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference
between the positive voltage V
T+
and the negative voltage V
T
is defined as the input
hysteresis voltage V
H
.
2. Features and benefits
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Wave and pulse shapers
Astable multivibrators
Monostable multivibrators
NXP Semiconductors
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC132N
74HCT132N
74HC132D
74HCT132D
74HC132DB
74HCT132DB
74HC132PW
74HCT132PW
40 C
to +125
C
TSSOP14
40 C
to +125
C
SSOP14
40 C
to +125
C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
plastic shrink small outline package; 14 leads; body
width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT108-1
SOT337-1
SOT402-1
40 C
to +125
C
Name
DIP14
Description
plastic dual in-line package; 14 leads (300 mil)
Version
SOT27-1
Type number
5. Functional diagram
1A
1Y
2
1B
3
1
4
2A
2Y
6
1
2
4
&
3
5
2B
9
3A
3Y
5
8
9
10
&
6
10
3B
&
8
12
4A
4Y
12
11
13
&
11
A
Y
B
mna409
13
4B
mna407
mna408
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one
Schmitt trigger)
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
2 of 20
NXP Semiconductors
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
mna406
14 V
CC
13 4B
12 4A
132
11 4Y
10 3B
9
8
3A
3Y
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
6.2 Pin description
Table 2.
Symbol
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
Pin description
Pin
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
Description
data input
data input
data output
ground (0 V)
supply voltage
7. Functional description
Table 3.
Input
nA
L
L
H
H
[1]
Function table
[1]
Output
nB
L
H
L
H
nY
H
H
H
L
H = HIGH voltage level; L = LOW voltage level; X = don’t care.
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
3 of 20
NXP Semiconductors
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
SO14, and (T)SSOP14
packages
[1]
[2]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
-
Max
+7
20
20
25
50
-
+150
750
500
Unit
V
mA
mA
mA
mA
mA
C
mW
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For DIP14 package: P
tot
derates linearly with 12 mW/K above 70
C.
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For (T)SSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
V
CC
V
I
V
O
T
amb
supply voltage
input voltage
output voltage
ambient temperature
Conditions
74HC132
Min
2.0
0
0
40
Typ
5.0
-
-
+25
Max
6.0
V
CC
V
CC
+125
74HCT132
Min
4.5
0
0
40
Typ
5.0
-
-
+25
Max
5.5
V
CC
V
CC
+125
V
V
V
C
Unit
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
4 of 20
NXP Semiconductors
74HC132; 74HCT132
Quad 2-input NAND Schmitt trigger
10. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
74HC132
V
OH
HIGH-level
output voltage
V
I
= V
T+
or V
T
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
I
O
=
4.0
mA; V
CC
= 4.5 V
I
O
=
5.2
mA; V
CC
= 6.0 V
V
OL
LOW-level
output voltage
V
I
= V
T+
or V
T
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
supply current
input
capacitance
HIGH-level
output voltage
V
I
= V
T+
or V
T
; V
CC
= 4.5 V
I
O
=
20 A
I
O
=
4.0
mA
V
OL
LOW-level
output voltage
V
I
= V
T+
or V
T
; V
CC
= 4.5 V
I
O
= 20
A;
I
O
= 4.0 mA;
I
I
I
CC
I
CC
input leakage
current
supply current
additional
supply current
V
I
= V
CC
or GND;
V
CC
= 5.5 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
per input pin;
V
I
= V
CC
2.1 V; I
O
= 0 A;
other inputs at V
CC
or GND;
V
CC
= 4.5 V to 5.5 V
-
-
-
-
-
-
0
0.15
-
-
30
0.1
0.26
0.1
2.0
108
-
-
-
-
-
0.1
0.33
1.0
20
135
-
-
-
-
-
0.1
0.4
1.0
40
147
V
V
A
A
A
4.4
3.98
4.5
4.32
-
-
4.4
3.84
-
-
4.4
3.7
-
-
V
V
V
I
= V
CC
or GND;
V
CC
= 6.0 V
V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
-
-
-
-
-
-
-
-
0
0
0
0.15
0.16
-
-
3.5
-
0.1
0.1
0.1
0.26
0.26
0.1
2.0
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.33
0.33
1.0
20
-
-
-
-
-
-
-
-
-
0.1
0.1
0.1
0.4
0.4
1.0
40
V
V
V
V
V
A
A
pF
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6.0
4.32
5.81
-
-
-
-
-
1.9
4.4
5.9
3.84
5.34
-
-
-
-
-
1.9
4.4
5.9
3.7
5.2
-
-
-
-
-
V
V
V
V
V
Conditions
Min
25
C
Typ
Max
40 C
to +85
C 40 C
to +125
C
Unit
Min
Max
Min
Max
74HCT132
V
OH
C
I
input
capacitance
3.5
-
-
-
-
-
pF
74HC_HCT132
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 30 August 2012
5 of 20
嵌入式系统
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