Product Brief
September 2004
™
FW323 06 T100
1394A
PCI PHY/Link Open Host Controller Interf
ace
Features
1394a-2000
OHCI link and PHY core function in a
single device:
— 100-pin TQFP package (also available in a lead-
free package*).
— Single-chip link and PHY enable smaller, simpler,
more efficient motherboard and add-in card
designs.
— Enables lower system costs.
— Leverages proven
1394a-2000
PHY core design.
— Demonstrated compatibility with current
Microsoft
Windows
®
drivers and common applications.
—
Demonstrated interoperability with existing, as well
as older,
1394
™
consumer electronics and periph-
erals products.
— Feature-rich implementation for high performance
in common applications.
— Supports low-power system designs (CMOS
implementation, power management features).
OHCI:
— Complies with the
1394 OHCI 1.1 Specification.
— OHCI 1.0 backwards compatible—configurable via
PCI bus commands to operate in either OHCI 1.0
or OHCI 1.1 mode.
— Complies with
Microsoft Windows
logo program
system and device requirements.
— Listed on
Windows
hardware compatibility list
http://www.microsoft.com/hcl/results.asp.
— Compatible with
Microsoft Windows
and
MacOS
®
operating systems.
— 4 Kbyte isochronous transmit FIFO.
— 2 Kbyte asynchronous transmit FIFO.
— 4 Kbyte isochronous receive FIFO.
— 2 Kbyte asynchronous receive FIFO.
— Dedicated asynchronous and isochronous
descriptor-based DMA engines.
— Eight isochronous transmit contexts.
— Eight isochronous receive contexts.
— Prefetches isochronous transmit data.
— Supports posted write transactions.
— Supports parallel processing of incoming physical
read and write requests.
— Supports notification (via interrupt) of a failed
register access.
1394a-2000
PHY core:
— Compliant with
IEEE
®
1394a-2000, Standard for a
High Performance Serial Bus
(Supplement).
* In an effort to better serve its customers and the environment,
Agere is switching to lead-free packaging on this product (no
intentional addition of lead).
— Provides three fully compliant cable ports, each
supporting 400 Mbits/s, 200 Mbits/s, and
100 Mbits/s traffic.
— Supports extended BIAS_HANDSHAKE time for
enhanced interoperability with camcorders.
— While unpowered and connected to the bus, will
not drive TPBIAS on a connected port even if
receiving incoming bias voltage on that port.
— Does not require external filter capacitor for PLL.
— Supports link-on as a part of the internal
PHY core-link interface.
— 25 MHz crystal oscillator and internal PLL provide
a
50 MHz
internal
link-layer controller clock as
well as
transmit/receive data at 100 Mbits/s,
200 Mbits/s, and 400 Mbits/s.
— Interoperable across
1394
cable with
1394
phys-
ical layers (PHY core) using 5 V supplies.
— Provides node power-class information signaling
for system power management.
— Supports ack-accelerated arbitration and fly-by
concatenation.
— Supports arbitrated short bus reset to improve
utilization of the bus.
— Fully supports suspend/resume.
— Supports connection debounce.
— Supports multispeed packet concatenation.
— Supports PHY pinging and remote PHY access
packets.
— Provides separate cable bias and driver termina-
tion voltage supply for each port.
Link:
— Cycle master and isochronous resource manager
capable.
— Supports
1394a-2000
acceleration features.
PCI:
— Revision 2.2 compliant.
— 33 MHz/32-bit operation.
— Programmable burst size thresholds for PCI data
transfer.
— Supports optimized memory read line, memory
read multiple, and memory write invalidate burst
commands.
— Supports
PCI Bus Power Management Interface
Specification
v.1.1.
— Global byte-swap function.
Note:
This device does not support D3cold wakeup,
NAND tree, EEPROM interface, CLKRUN
protocol,
mini PCI
®
applications, and CardBus
applications. Use the FW323 06 (128-pin) TQFP
or the FW323-T6 (120-pin) TQFP device if one or
more of these features are needed.
FW323 06 T100
1394A
PCI PHY/Link Open Host Controller Interface
Product Brief
September 2004
Features
(continued)
Other Features
CMOS process
3.3 V operation, 5 V tolerant inputs
100-pin TQFP package
FW323 Functional Overview
The FW323 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for imple-
mentation of
IEEE 1394a-2000
compliant systems and devices. Link-layer functions are handled by the FW323, uti-
lizing the on-chip
1394a-2000
compliant link core and physical layer core. A high-performance and cost-effective
solution for connecting and servicing multiple
IEEE 1394
(both
1394-1995
and
1394a-2000)
peripheral devices can
be realized using this PHY/link OHCI device.
OHCI
ASYNCHRONOUS
DATA
TRANSFER
PCI
BUS
PCI
CORE
CABLE PORT 2
LINK
CORE
PHY
CORE
CABLE PORT 1
CABLE PORT 0
ISOCHRONOUS
DATA
TRANSFER
OHCI
5-6250 (F).f
Figure 1. FW323 Conceptual Block Diagram
2
Agere Systems Inc.
Product Brief
September 2004
FW323 06 T100
1394A
PCI PHY/Link Open Host Controller Interface
FW323 Functional Description
The FW323 is comprised of four major functional sections (see
Figure 1):
PCI core, OHCI isochronous and
asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major
sections.
SLAVE
CONTROL
PCI SLAVE
ADDRESS/DATA
MUX
PCI BUS
MASTER
CONTROL
PCI MASTER
PCI
CONFIGURATION
Figure 2. PCI Core Block Diagram
PCI Core
The PCI core (shown in
Figure 2)
serves as the interface to the PCI bus. It contains the state machines that allow
the FW323 to respond properly when it is the target of the transaction. Also, during
1394
packet transmission or
reception, the PCI core arbitrates for the PCI bus and enables the FW323 to become the bus master for reading the
different buffer descriptors and management of the actual data transfers to/from host system memory.
The PCI core also supports the
PCI Bus Power Management Interface Specification
v.1.1. Included in this support
is a standard power management register interface accessible through the PCI configuration space. Through this
register interface, software is able to transition the FW323 into four distinct power states (D0, D1, D2, and D3hot).
This permits software to selectively increase/decrease the power consumption of the FW323 for reasons such as
periods of system inactivity or power conservation. In addition, the FW323 also includes support for waking up the
system through the generation of a power
management event (PME).
The FW323 supports generation of a power management event (PME) while in the D0, D1, D2, and D3hot power
states.
Agere Systems Inc.
3
FW323 06 T100
1394A
PCI PHY/Link Open Host Controller Interface
Product Brief
September 2004
FW323 Functional Description
(continued)
ASYNCHRONOUS DATA TRANSFER
SELFID DMA
ASYNC
RX
ADMIN
AR FIFO
PCI32 INTERFACE
ASYNC
REGISTER
ACCESS
PCI SLAVE
REGISTER
SELECT
ASYNC_RX
DMA
PHYSICAL
REQUEST/
RESPONSE
DMA
AT FIFO
ASYNC
TX
ADMIN
ASYNC_TX
DMA
OHCI
INTERRUPT
HANDLER
ISOCHRONOUS DATA TRANSFER
ISOCH
REGISTER
ACCESS
PCI MASTER
ARBITER
ISOCH
RECEIVE
DMA
IR FIFO
ISOCH
TRANSMIT
DMA
IT FIFO
Figure 3. OHCI Core Block Diagram
OHCI Data Transfer
The OHCI core consists of the three blocks shown in
Figure 3:
the PCI interface (PCI32_interface), the isochro-
nous data transfer, and the asynchronous data transfer blocks. The PCI interface provides an interface between
the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access
to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the
OHCI core and select data from appropriate sources. The PCI interface also has an OHCI interrupt handler to ser-
vice OHCI generated interrupts, which are ultimately translated into PCI interrupts.
OHCI Isochronous Data Transfer
The isochronous data transfer logic, which is incorporated into the OHCI core, handles the transfer of isochronous
data between the link core and the PCI interface module. It consists of the Isochronous register access module, the
isochronous transmit DMA module, the isochronous receive DMA module, the isochronous transmit (IT) FIFO, and
the isochronous receive (IR) FIFO.
4
Agere Systems Inc.
Product Brief
September 2004
FW323 06 T100
1394A
PCI PHY/Link Open Host Controller Interface
1394
isochronous channel. However, software can
select one context to receive data on multiple chan-
nels.
When IRDMA detects that the link core has placed data
into the receive FIFO, it immediately reads out the first
word in the FIFO, which makes up the header of the
isochronous packet. IRDMA extracts the channel
number for the packet and packet filtering controls from
the header. This information is compared with the
Control registers for each context to determine if any
context is to process this packet.
If a match is found, IRDMA will request access to the
PCI bus. When granted PCI access, a descriptor block
is fetched from host memory. The descriptor provides
information about the host memory block allocated for
the incoming packet. IRDMA then reads the packet
from the receive FIFO and writes the data to host
memory via the PCI bus.
If no match is found, IRDMA will read the remainder of
the packet from the receive FIFO, but not process the
data in any way.
FW323 Functional Description
(continued)
Isochronous Register Access
The Isochronous register access module services PCI
slave accesses to OHCI registers within the isochro-
nous block. The module also maintains the status of
interrupts generated within the isochronous block and
sends the isochronous interrupt status to the OHCI
interrupt handler block.
Isochronous Transmit DMA (ITDMA)
The isochronous transmit DMA (ITDMA) module
moves data from host memory to the link core, which
will then send the data via the PHY core to the
1394
bus. This module consists of eight isochronous
transmit contexts, each of which is independently
configurable by software, and is capable of sending
data on a separate
1394
isochronous channel.
During each
1394
isochronous cycle, the ITDMA
module will service each of the contexts and attempt to
process one
1394
packet for each active context. While
processing an active context, ITDMA will request
access to the PCI bus. When granted PCI access, a
descriptor block is fetched from host memory. This data
is decoded by ITDMA to determine how much data is
required and where in host memory the data resides.
ITDMA initiates another PCI access to fetch this data,
which is placed into the isochronous transmit FIFO for
processing by the link core. If the context is not active,
it is skipped by ITDMA for the current cycle.
After processing each context, ITDMA writes a cycle
marker word in the transmit FIFO to indicate to the link
core that there is no more data for this isochronous
cycle. As a summary, the major steps for the FW323
ITDMA to transmit a packet are the following:
1. Fetch a descriptor block from host memory.
2. Fetch data specified by the descriptor block from
host memory, and place it into the isochronous
transmit FIFO.
3. Data in FIFO is read by the link and sent to the PHY
core device interface.
Isochronous Receive DMA (IRDMA)
The isochronous receive DMA (IRDMA) module moves
data from the isochronous receive FIFO to host
memory. It consists of eight isochronous contexts, each
of which is independently controlled by software.
Normally, each context can process data on a single
OHCI Asynchronous Data Transfer
The asynchronous data transfer block within the OHCI
core is functionally partitioned into blocks responsible
for processing incoming SelfID packet streams, trans-
mitting and receiving asynchronous
1394
packets, pro-
cessing incoming physical request packets and
outgoing physical response packets, and servicing
accesses to OHCI registers within the respective asyn-
chronous blocks.
Asynchronous Register Access
The Asynchronous register access module operates on
PCI slave accesses to OHCI registers within the asyn-
chronous block. The module also maintains the status
of interrupts generated within the asynchronous block
and sends the asynchronous interrupt status to the
OHCI interrupt handler block.
Agere Systems Inc.
5
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