INTEGRATED CIRCUITS
CBT3857
10-bit bus switch with 10 kΩ pull-down
termination resistors
Product specification
Supersedes data of 1998 Dec 10
1999 Sep 14
Philips
Semiconductors
Philips Semiconductors
Product specification
10-bit bus switch with 10 kΩ pull-down
termination resistors
CBT3857
FEATURES
•
Enable signal is SSTL_2 compatible
•
Optimized for use in Double Data Rate (DDR) SDRAM
applications
DESCRIPTION
This 10-bit bus switch is designed for 3 V to 3.6 V V
CC
operation
and SSTL_2 output enable (OE) input levels.
When OE is LOW, the 10-bit bus switch is on and port A is
connected to port B. When OE is HIGH, the switch is open, and a
high-impedance state exists between the two ports.
The low on-state resistance of the switch allows connections to be
made with minimal propagation delay.
The CBT3857 is characterized for operation from 0°C to +85°C.
•
Flow-through architecture optimizes PCB layout
•
Designed to be used with 200 Mbps
•
Switch on resistance is designed to eliminate the need for series
resistor to DDR SDRAM
•
Internal 10 kΩ pull-down resistors on B port
•
Internal 50 kΩ pull-up resistor on output enable input
•
Full DDR solution provided when used with SSTL16857 and
PCK857
•
Latch-up protection exceeds 500 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
An to Yn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25°C; GND = 0 V
C
L
= 30 pF; V
CC
= 3.3 V
V
I
= 0 V or V
CC
Outputs disabled; V
O
= 0 V or V
CC
V
CC
= 3.6 V
TYPICAL
720
2.8
6.4
1
UNIT
ps
pF
pF
mA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
0°C to +85°C
ORDER CODE
CBT3857 PW
DWG NUMBER
SOT355–1
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
12
22, 21, 20, 19, 18,
17, 16, 15, 14, 13
23
24
SYMBOL
V
REF
A1–A10
GND
B1–B10
OE
V
CC
NAME AND FUNCTION
Reference output voltage
Inputs
Ground (V)
Outputs
Output enable
Positive supply voltage
V
REF
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
Vcc
OE
22
21
20
19
18
17
16
15
14
13
1999 Sep 14
ÎÎ
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
FUNCTION TABLE
INPUT
OE
L
H
H = High voltage level
L = Low voltage level
FUNCTION
A port = B port
Disconnect
SA00516
2
853–2168 22329
Philips Semiconductors
Product specification
10-bit bus switch with 10 kΩ pull-down
termination resistors
CBT3857
LOGIC DIAGRAM (POSITIVE LOGIC)
SIMPLIFIED SCHEMATIC, EACH FET SWITCH
A1
2
SW
R
INT
22
B1
A
B
11
A10
SW
R
INT
13
B10
OE
OE
V
REF
23
1
SA00518
SA00517
ABSOLUTE MAXIMUM RATINGS
1, 3
SYMBOL
V
CC
I
IK
V
I
T
stg
V
I
PARAMETER
DC supply voltage
DC input clamp current
DC input voltage range (OE
Storage temperature range
DC input voltage range (except OE)
2
only)
2
V
I/O
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
V
CC
+ 0.5
–65 to 150
–0.5 to 4.6
UNIT
V
mA
V
°C
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
REF
V
IH
V
IL
V
IH
V
IL
T
amb
DC supply voltage
Reference voltage (0.38 x V
CC
)
AC high-level input voltage
AC low-level Input voltage
DC high-level input voltage
DC low-level Input voltage
Operating free-air temperature range
0
V
REF
+
180 mV
V
REF
– 180 mV
+85
PARAMETER
LIMITS
Min
3
1.15
V
REF
+
350 mV
V
REF
– 350 mV
Typ
3.3
1.25
Max
3.6
1.35
UNIT
V
V
V
V
V
V
°C
NOTE:
1. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
1999 Sep 14
3
Philips Semiconductors
Product specification
10-bit bus switch with 10 kΩ pull-down
termination resistors
CBT3857
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
V
IK
PARAMETER
Input clamp voltage
TEST CONDITIONS
V
CC
= 3 V; I
I
= –18 mA
OE
I
I
Input leakage current
V
CC
= 3 6 V; V
I
= V
CC
or GND
3.6
A Port
B Port
V
REF
I
CC
C
I
Ci
O(OFF)
r
on2
r
off
2
T
amb
= 0°C to +85°C
Min
Typ
1
±0.73
±0.1
±20
±0.1
0.7
2.8
6.4
20
20
20
1
24
24
24
30
30
30
Max
–1.2
±500
±1
±500
±1
1.5
UNIT
V
µA
µA
µA
µA
mA
pF
pF
Ω
MΩ
Quiescent supply current
Control pins
Power-off leakage current
On-resistance
Off-resistance
V
CC
= 3.6 V; I
O
= 0, V
I
= V
CC
or GND
V
I
= 3 V or 0
V
O
= 3 V or 0; OE = V
CC
V
CC
= 3 V to 3.6 V; V
A
= 0.8 V; V
B
= 1.15 V
V
CC
= 3 V to 3.6 V; V
A
= 1.7 V; V
B
= 1.35 V
V
CC
= 3 V to 3.6 V; V
I
= 1.25 V; I
I
=
±10
mA
V
CC
= 3 V to 3.6 V; V
I
= 1.65 V
NOTES:
1. All typical values are at V
CC
= 3.3 V, T
amb
= 25°C
2. Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On–state resistance is
determined by the lowest voltage of the two (A or B) terminals.
AC CHARACTERISTICS
SYMBOL
t
pd
t
en
t
dis
PARAMETER
Propagation delay
1
enable
disable
FROM (INPUT)
A or B
OE
OE
TO (OUTPUT)
B or A
A or B
A or B
1
1
V
CC
= +3.3 V
±0.3
V
Min
Max
750
3
3
UNIT
ps
ns
ns
NOTE:
1. The propagation delay is based on the RC time constant of the typical on–state resistance of the switch and a load capacitance, when driven
by an ideal voltage source (zero output impedance); 24
Ω ×
30 pF.
184/200-pin DDR SDRAM DIMM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BACK SIDE
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT
CBT3857 (9)
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
FRONT SIDE
SSTL16857
SSTL16857
PCK857
The PLL clock distribution device and SSTL registered drivers reduce
signal loads on the memory controller and prevent timing delays and
waveform distortions that would cause unreliable operation
SDRAM
SW00393
1999 Sep 14
4
Philips Semiconductors
Product specification
10-bit bus switch with 10 kΩ pull-down
termination resistors
CBT3857
AC WAVEFORMS
V
M
= 1.5 V, V
IN
= GND to 3.0 V
2.75 V
1.375V
INPUT
0V
t
PLH
t
PHL
V
OH
1.25V
OUTPUT
V
OL
1.25V
1.375V
TEST CIRCUIT AND WAVEFORMS
4.3 V
From Output
Under Test
C
L
= 30 pF
500
Ω
S1
Open
GND
500
Ω
Load Circuit
TEST
t
pd
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
open
4.3 V
GND
SA00513
Waveform 1. Input (An) to Output (Yn) Propagation Delays
DEFINITIONS
Load capacitance includes jig and probe capacitance
C
L
=
V
IH
(AC)
Output Control
(Low-level
enabling
t
PZL
Output
Waveform 1
S1 at 4.3 V
(see Note)
t
PZH
Output
Waveform 2
S1 at Open
(see Note) *
SA00515
V
REF
t
PLZ
V
REF
V
IL
(AC)
3.5V
1.25 V
t
PHZ
V
OH
– 0.15V
1.25 V
0V
NOTES:
1. All input pulses are supplied by generators having the following
characteristics: PRR
≤
10 MHz, Z
O
= 50
Ω,
t
r
≤
2.5 ns, t
f
≤
2.5 ns.
2. The outputs are measured one at a time with one transition per
measurement.
V
OL
+ 0.15V
V
OL
V
OH
Note:
Waveform 1 is for an output with internal conditions such that
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
the output is high except when disabled by the output control.
* V
IH
= 3.0V with 25Ω input line impedance
SA00514
Waveform 2. 3-State Output Enable and Disable Times
1999 Sep 14
5
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