512Mb: x4, x8, x16 SDRAM
Features
SDR SDRAM
MT48LC128M4A2 – 32 Meg x 4 x 4 banks
MT48LC64M8A2 – 16 Meg x 8 x 4 banks
MT48LC32M16A2 – 8 Meg x 16 x 4 banks
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal, pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode
• Auto refresh
– 64ms, 8192-cycle refresh (commercial and
industrial)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
Options
• Configurations
– 128 Meg x 4 (32 Meg x 4 x 4 banks)
– 64 Meg x 8 (16 Meg x 8 x 4 banks)
– 32 Meg x 16 (8 Meg x 16 x 4 banks)
• Write recovery (
t
WR)
–
t
WR = 2 CLK
1
• Plastic package – OCPL
2
– 54-pin TSOP II (400 mil) (standard)
– 54-pin TSOP II (400 mil) Pb-free
• Timing – cycle time
– 7.5ns @ CL = 3 (PC133)
– 7.5ns @ CL = 2 (PC133)
• Self refresh
– Standard
– Low power
• Operating temperature range
– Commercial (0˚C to +70˚C)
– Industrial (–40˚C to +85˚C)
• Revision
Notes:
1. See technical note TN-48-05 on
Micron's Web site.
2. Off-center parting line.
3. Available on x4 and x8 only.
4. Contact Micron for availability.
Marking
128M4
64M8
32M16
A2
TG
P
-75
-7E
3
None
L
4
None
IT
:C
Table 1: Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
-7E
-75
-7E
-75
Clock
Frequency
143 MHz
133 MHz
133 MHz
100 MHz
Access Time
CL = 2
–
–
5.4ns
6ns
CL = 3
5.4ns
5.4ns
–
–
Setup Time
1.5ns
1.5ns
1.5ns
1.5ns
Hold Time
0.8ns
0.8ns
0.8ns
0.8ns
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. Q 12/12 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Features
Table 2: Address Table
Parameter
Configuration
Refresh count
Row addressing
Bank addressing
Column
addressing
32 Meg x 4
32 Meg x 4 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
4K A[9:0], A11, A12
32 Meg x 8
16 Meg x 8 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
2K A[9:0], A11
32 Meg
x 16
8 Meg x 16 x 4 banks
8K
8K A[12:0]
4 BA[1:0]
1K A[9:0]
Table 3: 512Mb SDR Part Numbering
Part Numbers
MT48LC128M4A2P
MT48LC128M4A2TG
MT48LC64M8A2P
MT48LC64M8A2TG
MT48LC32M16A2P
MT48LC32M16A2TG
Architecture
128 Meg x 4
128 Meg x 4
64 Meg x 8
64 Meg x 8
32 Meg x 16
32 Meg x 16
Package
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. Q 12/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Features
Contents
General Description ......................................................................................................................................... 6
Functional Block Diagrams ............................................................................................................................... 7
Pin and Ball Assignments and Descriptions ..................................................................................................... 10
Package Dimensions ....................................................................................................................................... 12
Temperature and Thermal Impedance ............................................................................................................ 13
Electrical Specifications .................................................................................................................................. 15
Electrical Specifications – I
DD
Parameters ........................................................................................................ 17
Electrical Specifications – AC Operating Conditions ......................................................................................... 18
Functional Description ................................................................................................................................... 21
Commands .................................................................................................................................................... 22
COMMAND INHIBIT .................................................................................................................................. 22
NO OPERATION (NOP) ............................................................................................................................... 23
LOAD MODE REGISTER (LMR) ................................................................................................................... 23
ACTIVE ...................................................................................................................................................... 23
READ ......................................................................................................................................................... 24
WRITE ....................................................................................................................................................... 25
PRECHARGE .............................................................................................................................................. 26
BURST TERMINATE ................................................................................................................................... 26
REFRESH ................................................................................................................................................... 27
AUTO REFRESH ..................................................................................................................................... 27
SELF REFRESH ....................................................................................................................................... 27
Truth Tables ................................................................................................................................................... 28
Initialization .................................................................................................................................................. 33
Mode Register ................................................................................................................................................ 35
Burst Length .............................................................................................................................................. 37
Burst Type .................................................................................................................................................. 37
CAS Latency ............................................................................................................................................... 39
Operating Mode ......................................................................................................................................... 39
Write Burst Mode ....................................................................................................................................... 39
Bank/Row Activation ...................................................................................................................................... 40
READ Operation ............................................................................................................................................. 41
WRITE Operation ........................................................................................................................................... 50
Burst Read/Single Write .............................................................................................................................. 57
PRECHARGE Operation .................................................................................................................................. 58
Auto Precharge ........................................................................................................................................... 58
AUTO REFRESH Operation ............................................................................................................................. 70
SELF REFRESH Operation ............................................................................................................................... 72
Power-Down .................................................................................................................................................. 74
Clock Suspend ............................................................................................................................................... 75
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. Q 12/12 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Features
List of Figures
Figure 1: 128 Meg x 4 Functional Block Diagram ............................................................................................... 7
Figure 2: 64 Meg x 8 Functional Block Diagram ................................................................................................. 8
Figure 3: 32 Meg x 16 Functional Block Diagram ............................................................................................... 9
Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 10
Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 12
Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 14
Figure 7: ACTIVE Command .......................................................................................................................... 23
Figure 8: READ Command ............................................................................................................................. 24
Figure 9: WRITE Command ........................................................................................................................... 25
Figure 10: PRECHARGE Command ................................................................................................................ 26
Figure 11: Initialize and Load Mode Register .................................................................................................. 34
Figure 12: Mode Register Definition ............................................................................................................... 36
Figure 13: CAS Latency .................................................................................................................................. 39
Figure 14: Example: Meeting
t
RCD (MIN) When 2 <
t
RCD (MIN)/
t
CK < 3 .......................................................... 40
Figure 15: Consecutive READ Bursts .............................................................................................................. 42
Figure 16: Random READ Accesses ................................................................................................................ 43
Figure 17: READ-to-WRITE ............................................................................................................................ 44
Figure 18: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 45
Figure 19: READ-to-PRECHARGE .................................................................................................................. 45
Figure 20: Terminating a READ Burst ............................................................................................................. 46
Figure 21: Alternating Bank Read Accesses ..................................................................................................... 47
Figure 22: READ Continuous Page Burst ......................................................................................................... 48
Figure 23: READ – DQM Operation ................................................................................................................ 49
Figure 24: WRITE Burst ................................................................................................................................. 50
Figure 25: WRITE-to-WRITE .......................................................................................................................... 51
Figure 26: Random WRITE Cycles .................................................................................................................. 52
Figure 27: WRITE-to-READ ............................................................................................................................ 52
Figure 28: WRITE-to-PRECHARGE ................................................................................................................. 53
Figure 29: Terminating a WRITE Burst ............................................................................................................ 54
Figure 30: Alternating Bank Write Accesses ..................................................................................................... 55
Figure 31: WRITE – Continuous Page Burst ..................................................................................................... 56
Figure 32: WRITE – DQM Operation ............................................................................................................... 57
Figure 33: READ With Auto Precharge Interrupted by a READ ......................................................................... 59
Figure 34: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 60
Figure 35: READ With Auto Precharge ............................................................................................................ 61
Figure 36: READ Without Auto Precharge ....................................................................................................... 62
Figure 37: Single READ With Auto Precharge .................................................................................................. 63
Figure 38: Single READ Without Auto Precharge ............................................................................................. 64
Figure 39: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 65
Figure 40: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 65
Figure 41: WRITE With Auto Precharge ........................................................................................................... 66
Figure 42: WRITE Without Auto Precharge ..................................................................................................... 67
Figure 43: Single WRITE With Auto Precharge ................................................................................................. 68
Figure 44: Single WRITE Without Auto Precharge ............................................................................................ 69
Figure 45: Auto Refresh Mode ........................................................................................................................ 71
Figure 46: Self Refresh Mode .......................................................................................................................... 73
Figure 47: Power-Down Mode ........................................................................................................................ 74
Figure 48: Clock Suspend During WRITE Burst ............................................................................................... 75
Figure 49: Clock Suspend During READ Burst ................................................................................................. 76
Figure 50: Clock Suspend Mode ..................................................................................................................... 77
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. Q 12/12 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2000 Micron Technology, Inc. All rights reserved.
512Mb: x4, x8, x16 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Address Table ..................................................................................................................................... 2
Table 3: 512Mb SDR Part Numbering ............................................................................................................... 2
Table 4: Pin and Ball Descriptions .................................................................................................................. 11
Table 5: Temperature Limits .......................................................................................................................... 13
Table 6: Thermal Impedance Simulated Values ............................................................................................... 14
Table 7: Absolute Maximum Ratings .............................................................................................................. 15
Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 15
Table 9: Capacitance ..................................................................................................................................... 16
Table 10: I
DD
Specifications and Conditions (-7E, -75) ..................................................................................... 17
Table 11: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) ............................. 18
Table 12: AC Functional Characteristics (-7E, -75) ........................................................................................... 19
Table 13: Truth Table – Commands and DQM Operation ................................................................................. 22
Table 14: Truth Table – Current State Bank
n,
Command to Bank
n
.................................................................. 28
Table 15: Truth Table – Current State Bank n, Command to Bank
m
................................................................. 30
Table 16: Truth Table – CKE ........................................................................................................................... 32
Table 17: Burst Definition Table ..................................................................................................................... 38
PDF: 09005aef809bf8f3
512Mb_sdr.pdf - Rev. Q 12/12 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2000 Micron Technology, Inc. All rights reserved.
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