SU564163578NWBS
August 4, 2006
Ordering Information
Module Part Numbers
SM564163578NWBS
SX564163578NWBS
SG564163578NWBS
Description
16Mx64 (128MB), SDRAM, 144-pin SODIMM, Unbuffered, Non-ECC, 16Mx16 Based,
PC133, CL 2.0 & 3.0, 25.40mm.
16Mx64 (128MB), SDRAM, 144-pin SODIMM, Unbuffered, Non-ECC, 16Mx16 Based,
PC133, CL 2.0 & 3.0, 25.40mm, Mixed Process Module.
16Mx64 (128MB), SDRAM, 144-pin SODIMM, Unbuffered, Non-ECC, 16Mx16 Based,
PC133, CL 2.0 & 3.0, 25.40mm, Green Module (RoHS Compliant).
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
1
SU564163578NWBS
August 4, 2006
Revision History
• August 4, 2006
Added SX564163578NWBS to the Ordering Information on page 1.
• November 4, 2005
Corrected the part numbers to SM564163578NWBS & SG564163578NWBS in the Ordering Information on page 1.
• September 7, 2005
Changed the datasheet part number from SM564163578NWBS to SU564163578NWBS because of the addition of a new
Module Process Technology.
Added SG564163578NWBS to the Ordering Information on page 1 because of the change in Module Process Technology.
Added SPD on pages 14, 15 & 16.
• February 26, 2002
Datasheet released.
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
2
SU564163578NWBS
August 4, 2006
128MByte (16Mx64) Synchronous DRAM Module - 16Mx16 Based
144-pin SODIMM, Unbuffered, Non-ECC
Features
•
•
•
•
•
•
•
Standard
Configuration
Cycle Time
CAS# Latency
Burst Length
Burst Type
No. of Internal
Banks per SDRAM
:
:
:
:
:
:
:
JEDEC
Non-ECC
7.5ns
2.0, 3.0
1, 2, 4, 8 or Page
Linear/Interleave
4
•
•
•
•
•
•
•
Operating Voltage :
3.3V
Refresh
:
8K/64ms
Device Physicals
:
400mil TSOP
Lead Finish
:
Gold
Length x Height
:
67.60mm x 25.40mm
No. of sides
:
Double-sided
Mating Connector (Examples)
Horizontal
:
AMP - 390113-1
144-pin SDRAM SODIMM Pin List
Pin
No.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
Pin
Name
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
V
SS
DQMB0
DQMB1
V
DD
A0
A1
A2
V
SS
Pin
No.
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
Pin
Name
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
V
SS
DQMB4
DQMB5
V
DD
A3
A4
A5
V
SS
Pin
No.
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
Pin
Name
DQ8
DQ9
DQ10
DQ11
V
DD
DQ12
DQ13
DQ14
DQ15
V
SS
NC
NC
CLK0
V
DD
RAS#
WE#
CS0#
NC
Pin
No.
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
Pin
Name
DQ40
DQ41
DQ42
DQ43
V
DD
DQ44
DQ45
DQ46
DQ47
V
SS
NC
NC
CKE0
V
DD
CAS#
NC
A12
NC
Pin
No.
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
Pin
Name
NC
V
SS
NC
NC
V
DD
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
DQ22
DQ23
V
DD
A6
A8
V
SS
Pin
No.
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
Pin
Name
CLK1
V
SS
NC
NC
V
DD
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
DQ54
DQ55
V
DD
A7
BA0
V
SS
Pin
No.
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Pin
Name
A9
A10/AP
V
DD
DQMB2
DQMB3
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
DD
Pin
No.
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Pin
Name
BA1
A11
V
DD
DQMB6
DQMB7
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
V
DD
(All specifications of this device are subject to change without notice.)
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
3
SU564163578NWBS
August 4, 2006
Pin Description Table
Symbol
CLK0, CLK1
CKE0
CS0#
RAS#, CAS#,
WE#
BA0, BA1
A0~A9,
A10/AP,
A11~A12
Type
Input
Input
Input
Input
Input
Input
Polarity
Positive
Edge
Active High
Active Low
Active Low
-
-
Function
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their associated
clock.
Activates the SDRAM CLK signal when high and deactivates the CLK signal when low. By deactivating
the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.
Enables the associated SDRAM command decoder when low and disables decoder when high. When
decoder is disabled, new commands are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, CAS#, RAS#, and WE# define the operations to be
executed by the SDRAM.
Selects which of the four internal SDRAM banks is activated.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at
the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8) when sampled at
the rising clock edge. In addition to the column address, A10/AP is used to invoke autoprecharge opera-
tion at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1
defines the bank to be precharged. If AP is low, autoprecharge is disabled.
During a Precharge command cycle, A10/AP is used in conjunction with BA0, BA1 to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If
AP is low, BA0 and BA1 are used to define which bank to precharge.
Data Input/Output pins.
Data strobe for input and output data.
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be con-
nected on the system board from the SDA bus line to V
DD
to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected on the
system board from the SCL bus line to V
DD
to act as a pullup.
Power and ground for the SDRAM input buffers and core logic.
No Connect.
DQ0~DQ63
DQMB0~
DQMB7
SDA
SCL
V
DD
, V
SS
NC
Input-
Output
Input
Input-
Output
Input
Supply
Supply
-
Active High
-
-
-
-
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
4
SU564163578NWBS
August 4, 2006
Block Diagram
CS0#
CKE0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
S# CKE
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U1
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
S# CKE
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U5
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
S# CKE
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U2
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
S# CKE
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
U4
DQMB
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Corporate Headquarters:
P. O. Box 1757, Fremont, CA 94538, USA • Tel:(510) 623-1231 • Fax:(510) 623-1434 • E-mail: info@smartm.com
Europe:
5 Kelvin Park South, Kelvin South, East Kilbride, G75 ORH, United Kingdom • Tel: +44-870-870-8747 • Fax: +44-870-870-8757
Asia/Pacific:
Plot 18, Lrg Jelawat 4, Kawasan Perindustrian Seberang Jaya 13700, Prai, Penang, Malaysia • Tel: +604-3992909 • Fax: +604-3992903
5
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