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74HC125
Quad 3−State Noninverting
Buffers
High−Performance Silicon−Gate CMOS
The 74HC125 is identical in pinout to the LS125. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
The HC125 noninverting buffer is designed to be used with 3−state
memory address drivers, clock drivers, and other bus−oriented
systems. The device has four separate output enables that are
active−low.
Features
14
1
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
1
HC125G
AWLYWW
•
•
•
•
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
ESD Performance: HBM
>
2000 V; Machine Model
>
200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are Pb−Free Devices
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HC
125
ALYWG
G
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G or
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
March, 2007
−
Rev. 0
1
Publication Order Number:
74HC125/D
74HC125
PIN ASSIGNMENT
OE1
A1
Y1
OE2
A2
Y2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
OE4
A4
Y4
OE3
A3
Y3
OE1
A2
OE2
A3
1
5
4
9
10
12
13
PIN 14 = V
CC
PIN 7 = GND
11
Y4
8
Y3
6
Y2
LOGIC DIAGRAM
HC125
Active−Low Output Enables
A1
2
3
Y1
FUNCTION TABLE
HC125
Inputs
A
H
L
X
OE
L
L
H
Output
Y
H
L
Z
OE3
A4
OE4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
I
out
I
CC
P
D
T
stg
T
L
V
out
Parameter
Value
Unit
V
V
V
mA
mA
mA
mW
_C
_C
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package)
SOIC Package†
TSSOP Package†
DC Output Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±20
±35
±75
500
450
– 65 to + 150
260
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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2
74HC125
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
in
, V
out
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
V
CC
+ 125
1000
500
400
Unit
V
V
_C
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Guaranteed Limit
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
v
20
mA
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
v
3.6 mA
|I
out
|
v
6.0 mA
|I
out
|
v
7.8 mA
3.0
4.5
6.0
6.0
6.0
– 55 to
25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
v
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
v
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1 V
|I
out
|
v
20
mA
V
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IH
|I
out
|
v
20
mA
V
in
= V
IH
V
V
OL
Maximum Low−Level Output
Voltage
V
in
= V
IL
|I
out
|
v
20
mA
V
in
= V
IL
I
in
I
OZ
Maximum Input Leakage Current
Maximum Three−State Leakage
Current
Maximum Quiescent Supply Current
(per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4.0
40
40
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
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3
74HC125
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
−
– 55 to
25_C
90
36
18
15
120
45
24
20
90
36
18
15
60
22
12
10
10
15
v
85_C
115
45
23
20
150
60
30
26
115
45
23
20
75
28
15
13
10
15
v
125_C
135
60
27
23
180
80
36
31
135
60
27
23
90
34
18
15
10
15
Unit
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
ns
C
in
C
out
Maximum Input Capacitance
Maximum 3−State Output Capacitance (Output in High−Impedance State)
pF
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
30
C
PD
Power Dissipation Capacitance (Per Buffer)*
pF
2
f + I
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
ORDERING INFORMATION
Device
74HC125DR2G
74HC125DTR2G
Package
SOIC−14
(Pb−Free)
TSSOP−14*
Shipping
†
2500 / Tape & Reel
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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4
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