PRELIMINARY
FEMTOCLOCK™ CRYSTAL-TO-
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
ICS843S2807
G
ENERAL
D
ESCRIPTION
ICS843S2807 is a low phase noise Clock Generator
and is a member of the HiperClockS™ family of high
HiPerClockS™
performance clock solutions from IDT. The device
provides five banks of outputs and a reference clock.
The banks can be enabled by using a common output
enable pin. A 25MHz crystal is used to generate the 50MHz,
66.67MHz, 87.5MHz, 100MHz, 125MHz, 133MHz and 350MHz
frequencies.
F
EATURES
•
Five banks of outputs:
Bank A:
one single-ended (QA0) LVCMOS output at: 133MHz
and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz
and 125MHz
Bank B:
two (QB0, QB1) LVCMOS outputs at: 50MHz
Bank C:
one (QC0/nQC0) differential LVPECL output at: 87.5MHz
Bank D:
one (QD0/nQD0) differential LVDS output at: 350MHz
One single-ended LVCMOS reference clock output at: 25MHz
•
Crystal input frequency: 25MHz
V
CCO
_
LVCMOS
IC
S
P
IN
A
SSIGNMENT
V
CCO
_
LVCMOS
REF_OUT
QB0
QB1
QA0
V
EE
V
EE
•
Maximum output frequency: 350MHz
•
±5% frequency margining
•
Full 3.3V operating supply
•
0°C to 70°C ambient operating temperature
24
V
CC
QA1
nQA1
V
CCA
1
V
EE
QC0
nQC0
V
CC
LVCMOS - 133MHz
32 31 30 29 28 27 26 25
F_SEL0
F_SEL1
V
CC
XTAL_IN
XTAL_OUT
V
EE
V
CCA
2
RESET
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MARGIN_MODE
PLL_BYPASS
OE
MARGIN
QD0
V
EE
nQD0
V
CC
•
Available in both standard (RoHS 5) and lead-free (RoHS6)
packages
ICS843S2807
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Top View
23
22
21
20
19
18
17
B
LOCK
D
IAGRAM
LVCMOS - 25MHz
REF_OUT
÷5.2631
F_SEL[1:0]
Pullup
PLL_BYPASS
Pulldown
2
QA0
1
25MHz
LVPECL - 66.67/100/
125MHz
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
700MHz
0
÷5.6,
÷7,
÷10.5
QA1
nQA1
LVCMOS - 50MHz
QB0
÷28
±5%
Frequency
Margining
÷14
QB1
LVPECL - 87.5MHz
QC0
÷8
nQC0
LVDS - 350MHz
QD0
MARGIN
Pulldown
MARGIN_MODE
Pulldown
RESET
Pulldown
OE
Pullup
÷2
nQD0
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT
™
/ ICS
™
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
1
ICS843S2807BY REV. A JANUARY 30, 2008
ICS843S2807
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR
PRELIMINARY
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1,
2
3, 16, 17, 24
4,
5
6, 13,
20, 27, 32
7, 21
8
9
10
11
12
14, 15
18, 19
22, 23
25, 30
26
Name
F_SEL0,
F_SEL1
V
CC
XTAL_IN,
XTAL_OUT
V
EE
V
CCA2,
V
CCA1
RESET
OE
MARGIN
MARGIN_MODE
PLL_BYPASS
QD0, nQD0
nQC0, QC0
nQA1, QA1
V
CCO_LVCMOS
QA0
Type
Input
Power
Input
Power
Power
Input
Input
Input
Input
Input
Output
Output
Output
Power
Output
Pullup
Pullup
Description
Frequency select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Core supply pins.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Negative supply pins.
Analog supply pins.
Pulldown Resets the dividers and PLL. LVCMOS/LVTTL interface levels.
Output enable pin. LVCMOS/LVTTL interface levels.
Selects between the margin and normal mode.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3B.
Selects between ±5% margin.
Pulldown
LVCMOS/LVTTL interface levels. See Table 3B.
Selects between the PLL and XTAL as the input to the dividers.
Pulldown When LOW, selects PLL. When HIGH, selects XTAL.
LVCMOS/LVTTL interface levels.
Differential Bank D clock outputs. LVDS interface levels.
Differential Bank C clock outputs. LVPECL interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output supply pins for LVCMOS/LVTTL outputs.
Single-ended Bank A clock output.
LVCMOS/LVTTL interface levels. 15
Ω
impedance.
Single-ended Bank B clock outputs.
28, 29
QB1, QB0
Output
LVCMOS/LVTTL interface levels. 15
Ω
impedance.
Reference clock output. LVCMOS/LVTTL interface levels.
31
REF_OUT
Output
15
Ω
impedance.
NOTE:
Pulldown
refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLDOWN
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power
Dissipation Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Output Impedance
QA0,
QB0, QB1,
REF_OUT
V
CCO_LVCMOS
= 3.465V
QA0,
QB0, QB1,
REF_OUT
V
CC
, V
CCO_LVCMOS
= 3.465V
Test Conditions
Minimum
Typical
4
TBD
51
51
15
Maximum
Units
pF
pF
kΩ
kΩ
Ω
IDT
™
/ ICS
™
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
2
ICS843S2807BY REV. A JANUARY 30, 2008
ICS843S2807
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR
PRELIMINARY
T
ABLE
3A. F_SEL
X
F
UNCTION
T
ABLE
Inputs
F_SEL1
0
1
1
F_SEL0
1
0
1
QA1 Output Frequency
(MHz)
100
125
66.67 (default)
T
ABLE
3B. MARGIN/MARGIN_MODE F
UNCTION
T
ABLE
Inputs
MARGIN
0
X
1
MARGIN_MODE
1
0
1
Operation
-5 %
Nominal
+5%
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
(LVCMOS)
Outputs, I
O
(LVDS)
Continuous Current
Surge Current
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Junction-to-Case
Storage Temperature, T
STG
50mA
100mA
71.9°C/W (0 mps)
-65°C to 150°C
10mA
15mA
4.6V
-0.5V to V
CC
+ 0.5V
-0.5V to V
CCO_LVCMOS
+ 0.5V
NOTE:
Stresses beyond those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of
product at these conditions or any conditions beyond those listed
in the
DC Characteristics
or
AC Characteristics
is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO_LVCMOS
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
CC
– I
CCA
* 10
Ω
3.135
Typical
3.3
3.3
3.3V
TBD
TBD
Maximum
3.465
V
CC
3.465
Units
V
V
V
mA
mA
IDT
™
/ ICS
™
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
3
ICS843S2807BY REV. A JANUARY 30, 2008
ICS843S2807
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR
PRELIMINARY
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
CC
= V
CCO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
V
IL
Input High Voltage
Input Low Voltage
Test Conditions
Minimum Typical
2
-0.3
Maximum
V
CC
+ 0.3
0.8
15 0
5
Units
V
V
µA
µA
µA
µA
V
0.5
V
PLL_BYPASS,
RESET, MARGIN,
V
CC
= V
IN
= 3.465V
Input
I
IH
MARGIN_MODE
High Current
OE, F_SEL[1:0]
PLL_BYPASS,
Input
RESET, MARGIN,
V
CC
= 3.465V, V
IN
= 0V
-5
I
IL
MARGIN_MODE
Low Current
OE, F_SEL[1:0]
-150
Output
REF_OUT,
2.6
V
OH
V
CCO_LVCMOS
= 3.465V±5%
High Voltage; NOTE 1 QA0, QB0, QB1
Output
REF_OUT,
V
OL
V
CCO_LVCMOS
= 3.465V±5%
Low Voltage; NOTE 1 QA0, QB0, QB1
NOTE 1: Outputs terminated with 50
Ω
to V
CCO_LVCMOS
/2. See Parameter Measurement Information,
Output Load Test Circuit diagram.
T
ABLE
4C. LVDS DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OD
Δ
V
OD
V
OS
Δ
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
Test Conditions
Minimum
Typical
400
50
1.25
50
Maximum
Units
mV
mV
V
mV
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Test Conditions
Minimum
V
CC
- 1.4
V
CC
- 2.0
0.6
Typical
Maximum
V
CC
- 0.9
V
CC
- 1.7
1.0
Units
V
V
V
NOTE 1: Outputs terminated with 50
Ω
to V
CC
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
Test Conditions
Minimum
Typical
25
50
7
1
Maximum
Units
MHz
Ω
pF
mW
Fundamental
IDT
™
/ ICS
™
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
4
ICS843S2807BY REV. A JANUARY 30, 2008
ICS843S2807
FEMTOCLOCK™ CRYSTAL-TO-LVPECL/LVDS/LVCMOS CLOCK GENERATOR
PRELIMINARY
T
ABLE
6. AC C
HARACTERISTICS
,
V
CC
= V
CCO_LVCMOS
= 3.3V ± 5%,T
A
= 0°C
TO
70°C
Symbol
Parameter
QD0/nQD0
QA0
QA1/nQA1
f
OUT
Output Frequency
QA1/nQA1
QA1/nQA1
QB0, QB1
QC0/nQC0
REF_OUT
Bank Skew;
NOTE 1, 2
F_SEL1 = 1, F_SEL0 = 1
F_SEL1 = 0, F_SEL0 = 1
F_SEL1 = 1, F_SEL0 = 0
Test Conditions
Minimum
Typical
350
133
66.67
10 0
125
50
87.5
25
TBD
75
150
75
200
50
Maximum
Units
MH z
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
55
55
55
%
%
%
t
sk(b)
QB0, QB1
REF_OUT
QA0
t
jit(cc)
Cycle-to-Cycle
Jitter; NOTE 2
QB0, QB1
QA1/nQA1
QC0/nQC0
QD0/nQD0
50
REF_OUT,
20% to 80%
350
QA0, QB0, QB1
Output
QA1/nQA1,
t
R
/ t
F
20% to 80%
250
Rise/Fall Time
QC0/nQC0
QD0/nQD0
20% to 80%
400
REF_OUT,
45
QA0, QB0, QB1
QA1/nQA1,
Output Duty Cycle
odc
45
QC0/nQC0
QD0/nQD0
45
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
IDT
™
/ ICS
™
LVPECL/LVDS/LVCMOS CLOCK GENERATOR
5
ICS843S2807BY REV. A JANUARY 30, 2008
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