MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Description
The MK2049-34A is a VCXO Phased Locked Loop
(PLL) based clock synthesizer that accepts multiple
input frequencies. With an 8 kHz clock input as a
reference, the MK2049-34A generates T1, E1, T3, E3,
ISDN, xDSL, and other communications frequencies.
This allows for the generation of clocks
frequency-locked and phase-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same
output for loop timing. All outputs are frequency locked
together and to the input.
This part also has a jitter-attenuated Buffer capability.
In this mode, the MK2049-34A is ideal for filtering jitter
from 27 MHz video clocks or other clocks with high
jitter.
ICS can customize these devices for many other
different frequencies.
Features
•
•
•
•
Packaged in 20-pin SOIC
3.3 V + 5% operation
Fixed I/O phase relationship on all selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4,
and 4E
Timing frequencies, or 10 to 36 MHz
•
Accepts multiple inputs: 8 kHz backplane clock, Loop
•
Locks to 8 kHz + 100 ppm (External mode)
•
Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
•
Exact internal ratios enable zero ppm error
•
Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and the OC3 submultiples
•
See the MK2049-01, -02, and -03 for more selections
at 5 V
Block Diagram
E
XTERNAL
P
ULLABLE
C
RYSTAL
(external loop filter)
I
NPUT
R
EFERENCE
C
LOCK
(T
YPICALLY
8
K
H
Z
)
VCXO-B
ASED
PLL
(M
ASTER
C
LOCK
G
ENERATOR
)
F
REQUENCY
M
ULTIPLYING
PLL
2
C
LOCK
O
UTPUT
C
LOCK
O
UTPUT
/ 2
8
K
H
Z
(R
EGENERATED
)
F
REQUENCY
S
ELECT
4
MDS 2049-34A A
Integrated Circuit Systems, Inc.
1
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Pin Assignment
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
FS0
RES
CAP2
GND
CAP1
VDD
GND
ICLK
FS3
FS2
20-pin (300) mil SOIC
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8k
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Pin
Type
Input
XO
XI
Power
-
Power
Power
Output
Output
Output
Input
Input
Input
Power
Power
Loop
Filter
Power
Loop
-
Input
Pin Description
Frequency select 1. Determines CLK input/outputs per table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Crystal connection. Connect to a MHz crystal as shown in table on page 3.
Power supply. Connect to +3.3 V.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
Power supply. Connect to +3.3 V.
Connect to ground
Clock output determined by status of FS3:0 per tables on page 3.
Clock output determined by status of FS3:0 per tables page 3. Always 1/2 of
CLK.
Recovered 8 kHz clock output.
Frequency select 2. Determines CLK input/outputs per tables on page 3.
Frequency select 3. Determines CLK input/outputs per tables on page 3.
Input clock connection. Connect to 8 kHz backplane or MHz clock.
Connect to ground.
Power Supply. Connect to +3.3 V.
Connect the loop filter ceramic capacitors and resistor between this pin and
CAP2.
Connect to ground.
Connect the loop filter ceramic capacitors and resistor between this pin and
Connect a 10-200kΩ resistor to ground. Contact ICS at telecom@icst.com for
recommended value for your application.
Frequency select 0. Determines CLK input/outputs per table on page 3.
MDS 2049-34A A
Integrated Circuit Systems, Inc.
2
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Output Decoding Table - External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
1
1
FS1
0
0
1
1
0
0
1
1
1
1
0
0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
CLK/2
1.544
2.048
22.368
17.184
19.44
16.384
17.664
18.688
7.68
10.752
10.24
38.88
CLK
3.088
4.096
44.736
34.368
38.88
32.768
35.328
37.376
15.36
21.504
20.48
77.76
8k
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
Crystal
Used (MHz)
12.352
12.288
11.184
11.456
9.72
8.192
17.664
9.344
15.36
10.752
10.24
9.72
N
1544
1536
1398
1432
1215
1024
2208
1168
1920
1344
1280
1215
Output Decoding Table - Loop Timing Mode (MHz)
ICLK
1.544
2.048
FS3
1
1
FS2
0
0
FS1
0
0
FS0
0
1
CLK/2
1.544
2.048
CLK
3.088
4.096
8k
N/A
N/A
Crystal
12.352
12.288
N
24
18
Output Decoding Table - Buffer Mode (MHz)
ICLK
19 - 36
10 - 18
FS3
1
1
FS2
1
1
FS1
1
1
FS0
0
1
CLK/2
ICLK/2
2*ICLK
CLK
ICLK
4*ICLK
8k
N/A
N/A
Crystal
ICLK/2
ICLK
N
3
3
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Operating Modes
The MK2049-34A has three operating modes: External, Loop Timing, and Buffer. Although each mode uses an
input clock to generate various output clocks, there are important differences in their input and crystal
requirements.
External Mode
The MK2049-34 accepts an external 8 kHz clock and will produce a number of common communication clock
frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10
ns is acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the
8 kHz ICLK; refer to Figure 1 on page 4 for more details.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1 and E1
inputs, the CLK/2 output will be the same as the input frequency, with CLK at twice the input frequency.
MDS 2049-34A A
Integrated Circuit Systems, Inc.
3
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider
range of input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of
getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27
MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
Input and Output Synchronization
As shown in the tables on page 3, the MK2049-34A offers a Zero Delay feature in all selections. There is an internal
feedback path between ICLK and the output clocks, providing a fixed phase relationship between the input and
output, a requirement in many communication systems.
The rising edge of ICLK will be aligned with the rising edges of CLK and CLK/2 (8 kHz is used in this illustration, but
the same is true for the selections in the Loop Timing and Buffer Modes).
IC L K (8 k H z )
C L K (M H z )
C L K /2 (M H z )
F ig u r e 1 . M K 2 0 4 9 -3 4 In p u t a n d O u tp u t C lo c k W a v e fo r m s
Measuring Zero Delay on the MK2049
The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth on the order of a
few Hertz. Since most 8 kHz input clocks will have high jitter, this can make measuring the input-to-output skew
(zero delay feature) very difficult. The MK2049 is designed to reject the input jitter; when the input and output clocks
are both displayed on an oscilloscope, they may
appear
not to be locked because the scope trigger point is
constantly changing with the input jitter. In fact, the input and output clocks probably are locked and the MK2049 will
have zero delay to the average position of the 8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input
clock is necessary. Most lab frequency sources are NOT SUITABLE for this since they have high jitter at low
frequencies.
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output
frequency as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For
example, if the crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary
by up to 60 ppm and still have the output clock remain frequency-locked.
MDS 2049-34A A
Integrated Circuit Systems, Inc.
4
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 032504
www.icst.com
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
PC Board Layout
A proper board layout is critical to the successful use of the MK2049-34A. In particular, the CAP1 and CAP2 pins
are very sensitive to noise and leakage (CAP2 at pin 18 is the most sensitive). Traces must be as short as possible
and the two capacitors and resistor must be mounted next to the device as shown below. The capacitor shown
between pins 15 and 17, and the one between pins 4 and 7 are the power supply decoupling capacitors. The high
frequency output clocks on pins 8 and 9 should have a series termination of 33Ω connected close to the pin.
Additional improvements will come from keeping all components on the same side of the board, minimizing vias
through other signal layers, and routing other signals away from the MK2049. You may also refer to application note
MAN05 for additional suggestions on layout of the crystal selection.
The crystal traces should include pads for small capacitors from X1 and X2 to ground. These are used to adjust the
stray capacitance of the board to match the crystal load capacitance. The typical telecom reference frequency is
accurate to much less than 1 ppm, so the MK2049-34A may lock and run properly even if the board capacitance is
not adjusted with these fixed capacitors. However, ICS recommends that the adjustment capacitors be included to
minimize the effects of variation in individual crystals, temperature, and aging. The value of these capacitors
(typically 0 - 4 pF) is determined once for a given board layout, using the procedure found in application note
MAN05 (http://www.icst.com/products/summary/man05.htm).
Cutout in ground and power plane.
Route all traces away from this area.
Optional -
see text
cap
G
cap
1
2
3
4
5
cap
cap
20
19
18
17
16
15
14
13
12
11
cap
resist
G
resist
V
G
cap
cap
6
7
8
9
10
V
resist
V
G
= connect to VDD
= connect to GND
resist
Figure 2. Typical MK2049-34 Layout
MDS 2049-34A A
Integrated Circuit Systems, Inc.
5
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 032504
www.icst.com
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