Datasheet> 器件分类 > 无源元件> 振荡器> SIT5346AICFQ733JQB19.123456X

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SIT5346AICFQ733JQB19.123456X: 产品描述Clipped Sine Output Oscillator, 19.123456MHz Nom, QFN-10; 产品类别无源元件振荡器; 文件大小2MB，共40页; 制造商SiTime; 标准

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SIT5346AICFQ733JQB19.123456X概述

Clipped Sine Output Oscillator, 19.123456MHz Nom, QFN-10

SIT5346AICFQ733JQB19.123456X规格参数

参数名称	属性值
是否Rohs认证	符合
Objectid	145140652047
包装说明	LCC10,.13X.2,58/52/48
Reach Compliance Code	unknown
老化	0.23 PPM/FIRST YEAR
频率调整-机械	NO
频率稳定性	0.1%
安装特点	SURFACE MOUNT
端子数量	10
标称工作频率	19.123456 MHz
最高工作温度	85 °C
最低工作温度	-40 °C
振荡器类型	CLIPPED SINE
输出阻抗	17 Ω
封装主体材料	CERAMIC
封装等效代码	LCC10,.13X.2,58/52/48
物理尺寸	5.15mm x 3.35mm x 1.06mm
最大压摆率	53 mA
最大供电电压	3.63 V
最小供电电压	2.97 V
标称供电电压	3.3 V
表面贴装	YES

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SiT5346

1 MHz – 60 MHz, ±0.1 to ±0.25 ppm,

Endura™ Series Precision Super-TCXO

Description

The

SiT5346

is a ruggedized ±100 ppb precision MEMS

Super-TCXO with a maximum acceleration sensitivity of

0.009 ppb/g or 0.1 ppb/g. Fully compliant to Telcordia GR-

1244-CORE Stratum 3 oscillator specifications, and

engineered for best dynamic performance, the SiT5346 is

ideal for high reliability defense, space, avionics, guidance,

precision GNSS and communications applications.

Leveraging SiTime’s unique DualMEMS™ temperature

sensing and TurboCompensation™ technologies, the

SiT5346 delivers the best dynamic performance for timing

stability in the presence of environmental stressors such as

air flow, temperature perturbation, vibration, shock, and

electromagnetic interference. This device also integrates

multiple on-chip regulators to filter power supply noise,

eliminating the need for a dedicated external LDO.

The SiT5346 offers three device configurations that can be

ordered using

Ordering Codes

for:

Features

◼

Any frequency from 1 MHz to 60 MHz in 1 Hz steps

Factory programmable options for short lead time

Best dynamic stability under airflow, thermal shock

▪

0.009 ppb/g or 0.1 ppb/g acceleration sensitivity

▪

±100 ppb stability across temperature

▪

±1 ppb/C typical frequency slope (ΔF/ΔT)

▪

1.5e-11 ADEV at 10 second averaging time

-40°C to +105°C operating temperature

No activity dips or micro jumps

Resistant to shock, vibration and board bending

On-chip regulators eliminate the need for external LDOs

Digital frequency pulling (DCTCXO) via I

▪

Digital control of output frequency and pull range

▪

Up to

±3200

ppm pull range

▪

Frequency pull resolution down to 5 ppt

2.5 V, 2.8 V, 3.0 V and 3.3 V supply voltage

LVCMOS or clipped sinewave output

RoHS and REACH compliant

Pb-free, Halogen-free, Antimony-free

Applications

◼

The SiT5346 can be factory programmed for any

combination of frequency, stability, voltage, and pull range.

Programmability enables designers to optimize clock

configurations while eliminating long lead times and

customization costs associated with quartz devices where

each frequency is custom built.

Refer to

Manufacturing Guideline

for proper reflow profile

and PCB cleaning recommendations to ensure best

performance.

◼

Ballistics, missiles, munitions

Military portable radios

Ruggedized communications networks

Precision GNSS systems

SATCOM

Transponders

Military, defense, space, avionics systems

Block Diagram

5.0 mm x 3.2 mm Package Pinout

SDA / NC

OE / VC / NC

SCL / NC

GND

VDD

CLK

A0 / NC

Figure 1. SiT5346 Block Diagram

Figure 2. Pin Assignments (Top view)

(Refer to

Table 13

for Pin Descriptions)

Rev 1.00

September 24, 2020

www.sitime.com

SiT5346

1 MHz – 60 MHz, ±0.1 to ±0.25 ppm, Endura™ Series Precision Super-TCXO

TABLE OF CONTENTS

Description ................................................................................................................................................................................... 1

Features....................................................................................................................................................................................... 1

Applications ................................................................................................................................................................................. 1

Block Diagram ............................................................................................................................................................................. 1

5.0 mm x 3.2 mm Package Pinout ............................................................................................................................................... 1

Ordering Information .................................................................................................................................................................... 2

Electrical Characteristics.............................................................................................................................................................. 4

Device Configurations and Pin-outs ........................................................................................................................................... 10

Pin-out Top Views............................................................................................................................................................... 10

Test Circuit Diagrams for LVCMOS and Clipped Sinewave Outputs ......................................................................................... 11

Waveforms................................................................................................................................................................................. 13

Timing Diagrams ........................................................................................................................................................................ 14

Stability Diagrams ...................................................................................................................................................................... 14

Typical Performance Plots ......................................................................................................................................................... 15

Architecture Overview ................................................................................................................................................................ 19

Frequency Stability ............................................................................................................................................................. 19

Output Frequency and Format ............................................................................................................................................ 19

Output Frequency Tuning ................................................................................................................................................... 19

Pin 1 Configuration (OE, VC, or NC) .................................................................................................................................. 20

Device Configurations ................................................................................................................................................................ 20

TCXO Configuration ........................................................................................................................................................... 20

VCTCXO Configuration ...................................................................................................................................................... 21

DCTCXO Configuration ...................................................................................................................................................... 22

VCTCXO-Specific Design Considerations ................................................................................................................................. 23

Linearity .............................................................................................................................................................................. 23

Control Voltage Bandwidth ................................................................................................................................................. 23

FV Characteristic Slope K

................................................................................................................................................. 23

Pull Range, Absolute Pull Range ........................................................................................................................................ 24

DCTCXO-Specific Design Considerations ................................................................................................................................. 25

Pull Range and Absolute Pull Range .................................................................................................................................. 25

Output Frequency ............................................................................................................................................................... 26

C Control Registers .......................................................................................................................................................... 28

Register Descriptions.......................................................................................................................................................... 28

Register Address: 0x00. Digital Frequency Control Least Significant Word (LSW) ............................................................ 28

Register Address: 0x01. OE Control, Digital Frequency Control Most Significant Word (MSW) ......................................... 29

[18]

........................................................................................ 30

Serial Interface Configuration Description .......................................................................................................................... 31

Serial Signal Format ........................................................................................................................................................... 31

Parallel Signal Format ........................................................................................................................................................ 32

Parallel Data Format ........................................................................................................................................................... 32

C Timing Specification ...................................................................................................................................................... 34

C Device Address Modes ................................................................................................................................................. 35

Schematic Example ............................................................................................................................................................ 36

Dimensions and Patterns ........................................................................................................................................................... 37

Layout Guidelines ...................................................................................................................................................................... 38

Manufacturing Guidelines .......................................................................................................................................................... 38

Additional Information ................................................................................................................................................................ 39

Revision History ......................................................................................................................................................................... 40

Rev 1.00

Page 3 of 40

www.sitime.com

SIT5346AICFQ733JQB19.123456X

SIT5346AICFQ733JQB19.123456X概述

SIT5346AICFQ733JQB19.123456X规格参数

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