0
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QPRO™ XQ4000XL Series QML
High-Reliability FPGAs
0
0*
DS029 (v1.2) February 9, 2000
XQ4000X Series Features
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Certified to MIL-PRF-38535 Appendix A QML (Qualified
Manufacturer Listing)
Ceramic and plastic packages
Also available under the following standard microcircuit
drawings (SMD)
- XQ4013XL 5962-98513
- XQ4036XL 5962-98510
- XQ4062XL 5962-98511
- XQ4085XL 5962-99575
For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
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Highest Capacity — Over 130,000 Usable Gates
Additional Routing Over XQ4000E
- almost twice the routing capacity for high-density
designs
Buffered Interconnect for Maximum Speed
New Latch Capability in Configurable Logic Blocks
Improved VersaRing™ I/O Interconnect for Better Fixed
Pinout Flexibility
- Virtually unlimited number of clock signals
Optional Multiplexer or 2-input Function Generator on
Device Outputs
5V tolerant I/Os
0.35
µ
m SRAM process
•
•
Available in -3 speed
System featured Field-Programmable Gate Arrays
- SelectRAM™ memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
Introduction
XQ4000X Series high-performance, high-capacity Field
Programmable Gate Arrays (FPGAs) provide the benefits
of custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Commercial XC4000X Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
networks
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System Performance beyond 50 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA Sink Current Per XQ4000XL Output
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
- Program verification
- Internal node observability
Development System runs on most common computer
platforms
- - Interfaces to popular design environments
- - Fully automatic mapping, placement and routing
- - Interactive design editor for design optimization
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DS029 (v1.2) February 9, 2000
1
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Table 1: XQ4000X Series High Reliability Field Progammable Gate Arrays
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
Logic
Cells
2432
3078
5472
7448
Max Logic Max. RAM
Typical Gate
Gates
Bits
Range
(No RAM) (No Logic) (Logic and RAM)*
13,000
36,000
62,000
85,000
18,432
41,472
73,728
100,352
10,000-30,000
22,000-65,000
40,000-130,000
55,000-180,000
CLB
Matrix
24x24
36x36
48x48
56x56
Total
CLBs
576
1,296
2,304
3,136
Number of
Flip-Flops
1,536
3,168
5,376
7,168
Max.
User I/O
192
288
384
448
Packages
PG223, CB228,
PQ240, BG256
PG411, CB228,
HQ240, BG352
PG475, CB228,
HQ240, BG432
PG475, CB228,
HQ240, BG432
* Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.
XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families.
Values are subject to change. Use as estimates, not for production.
Preliminary:
Based on preliminary characterization. Further changes are not expected.
Unmarked:
Specifications not identified as either Advance or Preliminary are to be considered final.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. For design
considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the
Xilinx W
EB
LINX at http://www.xilinx.com.
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
V
CCt
T
STG
T
SOL
T
J
Supply voltage relative to GND
Input voltage relative to GND (Note 1)
Voltage applied to 3-state output (Note 1)
Longest Supply Voltage Rise Time from 1 V to 3V
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Junction temperature
Ceramic Package
Plastic Package
Description
-0.5 to 4.0
-0.5 to 5.5
-0.5 to 5.5
50
-65 to +150
+260
+150
+125
Units
V
V
V
ms
°
C
°
C
°
C
°
C
Note 1: Maximum DC overshoot or undershoot above V
cc
or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts
less than 10 ns and with the forcing current being limited to 200 mA.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rat-
ings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is
not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2
DS029 (v1.2) February 9, 2000
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Recommended Operating Conditions
Symbol
Description
Supply voltage relative to GND, T
J
= -55
°
C to
+125
°
C
Supply voltage relative to GND, T
C
= -55
°
C to
+125
°
C
High-level input voltage
Low-level input voltage
Input signal transition time
Plastic
Ceramic
Min
3.0
3.0
50% of V
CC
0
Max
3.6
3.6
5.5
30% of V
CC
250
Units
V
V
V
V
ns
V
CC
V
IH
V
IL
T
IN
Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per ×C.
Note 2: Input and output measurement threshold is ~50% of V
CC
.
XQ4000XL DC Characteristics Over Recommended Operating Conditions
Symbol
V
OH
V
OL
V
DR
I
CCO
I
L
C
IN
I
RPU
I
RPD
I
RLL
Description
High-level output voltage @ I
OH
= -4.0 mA, V
CC
min (LVTTL)
High-level output voltage @ I
OH
= -500
µ
A, (LVCMOS)
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min (LVTTL) (Note 1)
Low-level output voltage @ I
OL
= 1500
µ
A, (LVCMOS)
Data Retention Supply Voltage (below which configuration data may be lost)
Quiescent FPGA supply current (Note 2)
Input or output leakage current
Input capacitance (sample tested)
BGA, PQ, HQ, packages
PGA packages
0.02
0.02
0.3
-10
2.5
5
+10
10
16
0.25
0.15
2.0
Min
2.4
90% V
CC
0.4
10% V
CC
Max
Units
V
V
V
V
V
mA
µ
A
pF
pF
mA
mA
mA
Pad pull-up (when selected) @ V
in
= 0 V (sample tested)
Pad pull-down (when selected) @ V
in
= 3.6 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
Note 1: With up to 64 pins simultaneously sinking 12 mA.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
DS029 (v1.2) February 9, 2000
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Speed Grade
Description
From pad through Global Low Skew buffer, to any clock K
Symbol
T
GLS
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
-3
Max
3.6
4.8
6.3
-
2.4
3.1
4.9
-
-1
Max
-
-
-
5.7
-
-
-
4.7
Units
ns
ns
ns
ns
ns
ns
ns
ns
From pad through Global Early buffer, to any IOB clock. Values are for
BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and
for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.
T
GE
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DS029 (v1.2) February 9, 2000
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000XL devices and expressed in nanoseconds unless otherwise noted.
Speed Grade
Description
Combinatorial Delays
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
C inputs via EC, DIN/H2 to YQ, XQ output (bypass)
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to C
OUT
Add/Subtract input (F3) to C
OUT
Initialization inputs (F1, F3) to C
OUT
C
IN
through function generators to X/Y outputs
C
IN
to C
OUT
, bypass function generators
Carry Net Delay, C
OUT
to C
IN
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
CIN input via F/G and H
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
Global Set/Reset
T
RPW
T
RIO
T
MRW
T
MRQ
F
TOG
3.0
3.7
19.8
166
2.5
2.8
15.0
200
ns
ns
ns
MHz
T
CH
T
CL
3.0
3.0
2.5
2.5
ns
ns
T
CKI
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
T
ICK
T
IHCK
T
HH0CK
T
HH1CK
T
HH2CK
T
DICK
T
ECCK
T
RCK
T
CCK
T
CHCK
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
OPCY
T
ASCY
T
INCY
T
SUM
T
BYP
T
NET
T
CKO
T
CKLO
2.7
3.3
2.0
2.8
0.26
0.32
2.1
2.1
2.0
2.5
1.5
2.4
0.20
0.25
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
ns
T
ILO
T
IHO
T
ITO
T
HH0O
T
HH1O
T
HH2O
T
CBYP
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.3
2.2
2.2
2.8
1.9
2.0
1.1
ns
ns
ns
ns
ns
ns
ns
Symbol
Min
-3
Max
Min
-1
Max
Units
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz)
(for export control)
See
page 14
for T
RRI
values per device.
DS029 (v1.2) February 9, 2000
5
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