XC61H
Series
Voltage Detector with Delay Circuit Built-In
ETR0212-003a
■GENERAL
DESCRIPTION
The XC61H series is a highly accurate, low power consumption CMOS voltage detector with a delay circuit. Detect voltage is
accurate with minimal temperature drift. Output configurations are available in both CMOS and N-channel open drain.
Since the full delay circuit is built-in, an external delay-time capacitor is not necessary so that high density mounting is possible.
■APPLICATIONS
●
Microprocessor reset circuitry
●
System battery life and charge voltage monitors
●
Memory battery back-up circuits
●
Power-on reset circuits
●
Power failure detection
●
Delay circuitry
■FEATURES
Detect Voltage Accuracy
: ± 2%
Low Power Consumption
: 1.0μA(TYP.)[ V
IN
=2.0V ]
: 1.6V ~ 6.0V (0.1V increments)
Detect Voltage Range
Operating Voltage Range
: 0.7V ~ 10.0V
Detect Voltage Temperature Characteristics
: ±100ppm/℃(TYP.)
Built-In Release Delay time
: 1ms (MIN.)
50ms (MIN.)
80ms (MIN.)
Output Configuration
: N-ch open drain or CMOS
Package
: SOT-23
Environmentally Friendly
: EU RoHS Compliant, Pb Free
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE
CHARACTERISTICS
μP
V
IN
R pull
●Release
Delay Time (t
DR
) vs. Ambient Temperature
ＸＣ６１ＨＣ３０１２
Release Delay Time: t
DR
(ms)
RESETB
2
V
IN
3
V
SS
1
RESETB
INPUT
V
SS
XC61HN series
Rpull is
Not necessary with CMOS output products
not necessary with CMOS output products
Ambient Temperature: Ta (℃)
1/13
XC61H
Series
■PIN
CONFIGURATION
■PIN
ASSIGNMENT
PIN NUMBER
SOT-23
1
2
3
（TOP
VIEW）
PIN NAME
V
SS
FUNCTION
Ground
Output
Supply Voltage Input
RESETB
V
IN
■PRODUCT
CLASSIFICATION
●Ordering
Information
XC61H
①②③④⑤⑥⑦-⑧
(*1)
DESIGNATOR
①
②③
④
⑤
⑥⑦-⑧
(*1)
ITEM
Output Configuration
Detect Voltage (V
DF
)
Release Delay Time
Detect Accuracy
Package
(Oder Unit)
SYMBOL
C
N
16 ~ 60
1
4
5
2
MR-G
CMOS output
N-ch open drain output
e.g. 2.5V
→ ②2
,
③5
50ms ~ 200ms
80ms ~ 400ms
1ms ~ 50ms
±
2.0%
(*2)
SOT-23 (3000/Reel)
DESCRIPTION
(*1) The ”-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
(*2)
No parts are available with an accuracy of ± 1%
■BLOCK
DIAGRAMS
(1)CMOS output
(2)N-ch open drain output
2/14
XC61H
Series
■ABSOLUTE
MAXIMUM RATINGS
PARAMETER
Input Voltage
Output Current
CMOS
Output Voltage
N-ch open drain
Power Dissipation
SOT-23
Operating Temperature Range
Storage Temperature Range
SYMBOL
V
IN
I
OUT
RESTB
Pd
Topr
Tstg
RATINGS
12.0
50
V
SS
-0.3 ~V
IN
+0.3
V
SS
-0.3 ~ 12
250
-30½+80
-40½+125
Ta=25℃
UNITS
V
mA
V
mW
℃
℃
■ELECTRICAL
CHARACTERISTICS
PARAMETER
Detect Voltage
Hysteresis Width
SYMBOL
V
DF
V
HYS
V
IN
= 1.5V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
DF
=1.6V½6.0V
V
IN
= 1.0V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
IN
= 8.0V
-
I
LEAK
Nch Open Drain
Detect Voltage
Temperature Characteristics
Release Delay Time
(V
DR
→
RESEB inversion)
ΔV
DF
ΔTopr½V
DF
t
DR
V
IN
changes from 0.6V to 10V
V
IN
=10.0V, V
OUT
=10.0V
-
-
50
80
1
0.01
±100
-
-
-
0.1
-
200
400
50
ppm/℃
ms
CONDITIONS
MIN.
V
DF(T)
x 0.98
V
DF
x 0.02
-
-
-
-
-
0.7
1.0
3.0
5.0
6.0
7.0
TYP.
V
DF(T)
V
DF
x 0.05
0.9
1.0
1.3
1.6
2.0
-
2.2
7.7
10.1
11.5
13.0
-10.0
0.01
MAX.
V
DF(T)
x 1.02
V
DF
x 0.08
2.6
3.0
3.4
3.8
4.2
10.0
-
-
-
-
-
-2.0
-
μA
UNITS
V
V
Ta = 25℃
CIRCUIT
①
①
Supply Current
(*1)
I
SS
μA
②
Operating Voltage
V
IN
V
①
Output Current
I
OUT
N-ch, V
DS
= 0.5V
③
mA
P-ch, V
DS
=2.1V
(CMOS Output)
Leakage
Current
CMOS Output
④
③
-
⑤
V
DF
(T) is nominal detect voltage value
Release Voltage: V
DR
= V
DF
+ V
HYS
(*1) The supply current during power-start until output being stable (during release operation) is 2μA greater with comparison to the period
after the completion of release operation because of the shoot-through current in delay current.
3/13
XC61H
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
An input voltage V
IN
starts higher than the release voltage V
DR
. Then, V
IN
voltage will gradually fall. When V
IN
voltage is
higher than detect voltage V
DF
, output voltage RESETB is equal to the V
IN
voltage.
*Note that high impedance exists at RESETB with the N-channel open drain configuration. If the RESETB pin is pulled
up, RESETB will be equal to the pull up voltage.
②
When V
IN
falls below V
DF
, RESETB will be equal to ground voltage V
SS
level (detect state).
* Note that this also applies to N-channel open drain configurations.
③
When VI
N
falls to a level below that of the minimum operating voltage V
MIN,
output will become unstable.
*When the output pin is generally pulled up with N-channel open drain configurations, output will be equal to pull up
voltage.
④
When V
IN
rises above the V
SS
level (excepting levels lower than minimum operating voltage), RESETB will be equal to
V
SS
until V
IN
reaches the V
DR
level.
⑤
Although V
IN
will rise to a level higher than V
DR
, RESETB maintains ground voltage level via the delay circuit.
⑥
After taking a release delay time, V
IN
voltage will be output at the RESETB pin.
*High impedance exists with the N-channel open drain configuration and that voltage will be dependent on pull up.
①
Notes:
1. The difference between V
DR
and V
DF
represents the hysteresis width.
2. Release delay time (
t
DR
) represents the time it takes until when V
IN
voltage appears at RESETB pin once the input
voltage has exceeded the V
DR
level.
●Timing
Chart
Output Voltage (RESETB)
Release Delay Time (t
DR
)
4/14
XC61H
Series
■NOTES
ON USE
1. Please use this IC within the stated maximum ratings. The IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the V
IN
pin and the input with CMOS output configurations, irregular oscillation
may occur as a result of voltage drops at R
IN
if load current (I
OUT
) exists. It is therefore recommend that no resistor be
added. (refer to Figure 1 below)
3. When a resistor is connected between the V
IN
pin and the input with CMOS output configurations, irrespective of N-ch
output configurations, oscillation may occur as a result of shoot-through current at the time of voltage release even if
load current (I
OUT
) does not exist. (refer to Figure 1 below)
4. By connecting a resistor between the V
IN
pin and the input, detect and release voltages will rise as a result of the IC's
supply current flowing through the V
IN
pin.
5. If a resistor (R
IN
) must be used, then please use with as small a level of input impedance as possible in order to control
the occurrences of oscillation as described above.
Further, please ensure that R
IN
is less than 10kΩ and that C
IN
is more than 0.1μF (Figure 1). In such cases, detect
and release voltages will rise due to voltage drops at R
IN
brought about by the IC's supply current.
6. Depending on circuit's operation, release delay time of this IC can be widely changed due to upper limits or lower limits
of operational ambient temperature.
●
Irregular Oscillations
(1) Irregular oscillation as a result of output current with the CMOS output configuration:
When the voltage applied at IN rises, release operations commence and the detector's output voltage increases.
Load current (I
OUT
) will flow through R
L
. Because a voltage drop (R
IN
x I
OUT
) is produced at the R
IN
resistor, located
between the input (IN) and the V
IN
pin, the load current will flow via the IC's V
IN
pin. The voltage drop will also lead to
a fall in the voltage level at the V
IN
pin. When the V
IN
pin voltage level falls below the detect voltage level, detect
operations will commence. Following detect operations, load current flow will cease and since voltage drop at R
IN
will
disappear, the voltage level at the V
IN
pin will rise and release operations will begin over again.
Irregular oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Irregular oscillation as a result of shoot-through current:
Since the XC61H series are CMOS IC
S
, shoot-through current will flow when the IC's internal circuit switching
operates (during release and detect operations). Consequently, irregular oscillation is liable to occur during release
voltage operations as a result of output current which is influenced by this shoot-through current (Figure 3).
Since hysteresis exists during detect operations, irregular oscillation is unlikely to occur.
XC61HN Series
XC61HC Series
図 1．入力抵抗を入れた時の回路例
Figure 1 Use of input resistor R
IN
5/13
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