Data Sheet
PT7C4512 PLL Clock Multiplier
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Features
• Zero ppm multiplication error
• Input crystal frequency of 5 - 40 MHz
• Input clock frequency of 4 - 50 MHz
• Output clock frequencies up to 200 MHz
• Low period jitter 80ps (100~200MHz)
• Duty cycle 45/55% of output clock
• 9 selectable frequencies controlled by S0, S1 pins
• Operating voltages of 3.0 to 5.5V
Description
This serial is the most effective cost way to generate a
high quality, high frequency clock output from lower fre-
quency crystal or clock input. It is designed to replace
crystal oscillators in most electronic systems, clock mul-
tiplier and frequency translation with low output jitter.
Using PLL techniques, the device uses a standard fun-
damental mode, inexpensive crystal to produce output
clocks up to 200 MHz.
The internal Logic divider is to generate nine different
Pa ck a ge
8 - Pin SOIC
Lead free 8 - Pin SOIC
Ordering Information
Pa r t Numbe r
PT7C4512W
PT7C4512WE
popular multiplication factors, allowing one chip to output
many common frequencies.
Block Diagram
S0
S1
PLL Clock Synthesis
and
Control Circuit
Output
Buffer
CLK
X1/ICLK
X2
Crystal
Oscillator
Output
Buffer
REF
V
CC
GND
PT0152(09/07)
1
Ver:3
Data Sheet
PT7C4512 PLL Clock Multiplier
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Pin Assignment
1
2
3
4
X1/ICLK
Vcc
GND
REF
X2
S1
S0
CLK
8
7
6
5
SOIC-8 package
Pin Description
Pin
1
2
3
4
5
6
7
8
Name
X1/ICLK
Vcc
GND
REF
CLK
S0
S1
X2
Type
I
P
P
O
O
I
I
O
Description
Crystal connection or clock input.
Connect to +3.3V or +5V.
Ground
Buffered crystal oscillator output clock
Clock output per table below
Multiplier select pin 0. Connect to GND or Vcc or float (no connection)
Multiplier select pin 1. Connect to GND or Vcc or float (no connection)
Crystal connection. Leave unconnected for clock input.
Clock Output Table
S1
0
0
0
S0
0
M
2)
1
CLK
x 4
1)
x (16/3)
x5
M
0
x 2.5
M
M
x2
M
1
x (10/3)
1
0
x6
1
M
x3
1
1
x8
1) Note:
CLK output frequency = ICLK x 4.
2) Note:
M = leave unconnected (self-biases to Vcc/2).
PT0152(09/07)
2
Ver:3
Data Sheet
PT7C4512 PLL Clock Multiplier
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested)
Note:
Stresses greater than those listed under MAXI-
Storage temperature ........................................................... -65 to 150
O
C
MUM RATINGS may cause permanent damage to
Ambient Operating Temperature .......................................... -40 to 85
O
C
the device. This is a stress rating only and func-
Supply Voltage to Ground Potential (V
CC
) .......................... -0.3 to +7.0V
tional operation of the device at these or any other
Inputs (Referenced to GND) ........................................ -0.5 to Vcc+0.5V
conditions above those indicated in the operational
Clock Output (Referenced to GND) .............................. -0.5 to Vcc+0.5V
sections of this specification is not implied. Expo-
Soldering Temperature (Max of 10 seconds) ............... 260
O
C (Max.10s)
sure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
Recommended Operation Conditions
Sym.
V
CC
T
A
Description
Supply Voltage
Operating Temperature
Test conditions
-
-
Min
3
-40
Typ
-
-
Max
5.5
85
Unit
V
°C
DC Electrical Characteristics
O
Sym
Vcc
Icc
V
IH
V
IL
V
IH
V
IM
V
IL
V
OH
V
OL
I
S
Parameter
Supply Voltage
Supply Current
Input Logic High
Input Logic Low
Input Logic High
Input mid-level
Input Logic Low
High-level output voltage
Low-level output voltage
Short Circuit Current
(V
CC
= 3.3V
±
0.3V, T
A
= 0~70 C, unless otherwise noted)
Test Conditions
-
no load, 20MHz crystal
-
-
-
-
-
I
OH
= -12mA
I
OL
= 12mA
-
Pin
Vcc
Vcc
ICLK
ICLK
S0, S1
S0, S1
S0, S1
CLK, REF
CLK, REF
CLK
Min
3
-
(Vcc/2)+1
-
Vcc-0.5
-
-
2.4
-
-
Typ
-
12
Vcc/2
Vcc/2
-
Vcc/2
-
-
-
±
70
Max
5.5
20
-
(Vcc/2)-1
-
-
0.5
-
0.4
-
Unit
V
mA
V
V
V
V
V
V
V
mA
PT0152(09/07)
3
Ver:3
Data Sheet
PT7C4512 PLL Clock Multiplier
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AC Electrical Characteristics
(V
CC
= 3.3V
±
0.3V, T
A
=-40~85 C, unless noted)
O
Sym. Parameter
f
IN
Input Frequency
Test Condition
crystal
clock
Pin
ICLK
ICLK
CLK
CLK
CLK
CLK
CLK
-
CLK
Min.
5
4
20
20
-
-
45
10
-
Typ.
-
-
-
-
1
1
50
-
80
Max.
40
50
200
180
-
-
55
-
100
Unit
MHz
MHz
MHz
MHz
ns
ns
%
kHz
ps
f
OUT
Output frequency**
V
CC
: 4.5 to 5.5V
V
CC
: 3.0 to 3.6V
t
r
t
f
Output clock rise time
Output clock fall time
0.8 to 2.0V,
with 15pF load
2.0 to 0.8V,
with 15pF load
At V
CC
/2
-
100MHz~200MHz
Duty Output clock duty cycle
PLL bandwidth*
Period Jitter
*
only reference for design
** The phase relationship between input and output clocks can change at power up.
PT0152(09/07)
4
Ver:3
Data Sheet
PT7C4512 PLL Clock Multiplier
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Mechanical Information
W/WE (SOIC-8)
8
.149
.157
3.78
3.99
1
.189
.196
4.80
5.00
.0099
.0196
0.25
0.50
x 45
o
0-8
o
.0075
.0098
0.40
1.27
.016
.050
0.19
0.25
.016
.026
0.406
0.660
REF
.050
BSC
1.27
.013
.020
.053
.068
1.35
1.75
SEATING PLANE
.2284
.2440
5.80
6.20
.0040
.0098
0.330
0.508
0.10
0.25
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Note:
1) Controlling dimensions in millimeters.
2) Ref: JEDEC MS-012 AA
PT0152(09/07)
5
Ver:3
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