Preliminary
CAT24WC03/05/09/17
2K/4K/8K/16K-Bit Serial E
2
PROM
FEATURES
s
400 KHZ I
2
C Bus Compatible*
s
1.8 to 6.0Volt Operation
s
Low Power CMOS Technology
s
Write Protect Feature
s
Self-Timed Write Cycle with Auto-Clear
s
1,000,000 Program/Erase Cycles
s
100 Year Data Retention
s
8-pin DIP, 8-pin SOIC and 8-pin TSSOP Package
s
Commercial, Industrial and Automotive
–Top 1/2 Array Protected When WP at V
IH
s
16-Byte Page Write Buffer
Temperature Ranges
DESCRIPTION
The CAT24WC03/05/09/17 is a 2K/4K/8K/16K-bit Serial
CMOS E
2
PROM internally organized as 256/512/1024/
2048 words of 8 bits each. Catalyst’s advanced CMOS
technology substantially reduces device power require-
ments. The CAT24WC03/05/09/17 features a 16-byte
page write buffer. The device operates via the I
2
C bus
serial interface, has a special write protection feature,
and is available in 8-pin DIP or 8-pin SOIC
PIN CONFIGURATION
DIP Package (P)
A0
A1
A2
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
A0
A1
A2
VSS
BLOCK DIAGRAM
SOIC Package (J)
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
TSSOP Package (U)
(** Available for 24WC03 only)
SDA
VCC
WP
SCL
SDA
WP
START/STOP
LOGIC
A0
A1
A2
VSS
1
2
3
4
SS
8
7
6
5
XDEC
CONTROL
LOGIC
E
2
PROM
PIN FUNCTIONS
Pin Name
A0, A1, A2
SDA
SCL
WP
V
CC
V
SS
Function
Device Address Inputs
Serial Data/Address
Serial Clock
Write Protect
+1.8V to +6.0V Power Supply
Ground
A0
A1
A2
SLAVE
ADDRESS
COMPARATORS
SCL
STATE COUNTERS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24WCXX F03
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
1,000,000
100
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Limits
Symbol
I
CC
I
S(5)
I
LI
I
LO
V
IL
V
IH
V
OL1
V
OL2
Parameter
Power Supply Current
Standby Current (V
CC
= 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3.0V)
Output Low Voltage (V
CC
= 1.8V)
–1
V
CC
x 0.7
Min.
Typ.
Max.
3
0
10
10
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
mA
µA
µA
µA
V
V
V
V
I
OL
= 3 mA
I
OL
= 1.5 mA
Test Conditions
f
SCL
= 100 KHz
V
IN
= GND or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
I/O(3)
C
IN(3)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
8
6
Units
pF
pF
Conditions
V
I/O
= 0V
V
IN
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Standby Current (I
SB
) = 0µA (<900nA).
Doc. No. 25063-00 2/98 S-1
2
Preliminary
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
CAT24WC03/05/09/17
Read & Write Cycle Limits
Symbol
Parameter
1.8V, 2.5V
Min.
F
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(1)
t
F(1)
t
SU:STO
t
DH
Clock Frequency
Noise Suppression Time
Constant at SCL, SDA Inputs
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
4
100
4.7
4
4.7
4
4.7
0
50
1
300
0.6
100
Max.
100
200
3.5
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
4.5V-5.5V
Min.
Max.
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
Power-Up Timing
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
1
1
Units
ms
ms
Write Cycle Limits
Symbol
t
WR
Parameter
Write Cycle Time
Min.
Typ.
Max
10
Units
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
3
Doc. No. 25063-00 2/98 S-1
CAT24WC03/05/09/17
Preliminary
FUNCTIONAL DESCRIPTION
The CAT24WC03/05/09/17 supports the I
2
C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC03/05/
09/17 operates as a Slave device. Both the Master and
Slave devices can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated. A maximum of 8 devices (24WC03), 4 devices
(24WC05), 2 devices (24WC09) and 1 device (24WC17)
may be connected to the bus as determined by the
device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24WC03/05/09/17 serial clock input pin is used
to clock all data transfers into or out of the device. This
is an input pin.
SDA:
Serial Data/Address
The CAT24WC03/05/09/17 bidirectional serial data/ad-
dress pin is used to transfer data into and out of the
device. The SDA pin is an open drain output and can be
wire-ORed with other open drain or open collector
outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
using 24WC03 device. All three address pins are used
Figure 1. Bus Timing
tF
tLOW
tHIGH
tLOW
tR
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
SDA IN
tAA
SDA OUT
5020 FHD F03
tDH
tBUF
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
5020 FHD F05
Doc. No. 25063-00 2/98 S-1
4
Preliminary
for 24WC03. If only one 24WC03 is addressed on the
bus, all three address pins (A0, A1, and A2) can be left
floating or connected to V
SS
A total of four devices can be addressed on a single bus
when using 24WC05 device. Only A1 and A2 address
pins are used with this device. The A0 address pin is a
no connect pin and can be tied to V
SS
or left floating. If
only one 24WC05 is being addressed on the bus, the
address pins (A1 and A2) can be left floating or con-
nected to V
SS
.
Only two devices can be cascaded when using 24WC09.
The only address pin used with this device is A2. The A0
and A1address pins are no connect pins and can be tied
to V
SS
or left floating. If only one 24WC09 is being
addressed on the bus, the address pin (A2) can be left
floating or connected to V
SS
.
The 24WC17 is a stand alone device. In this case, all
address pins (A0, A1and A2) are no connect pins and
can be tied to V
SS
or left floating.
WP:
Write Protect
If the WP pin is tied to V
CC
the upper half of memory array
becomes Write Protected (READ only)(locations 80H to
FFH for 24WC03, locations 100H to 1FFH for 24WC05,
locations 200H to 3FFH for 24WC09, locations 400H to
7FFH for 24WC17). When the WP pin is tied to V
SS
or
left floating normal read/write operations are allowed to
the device.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
CAT24WC03/05/09/17
I
2
C BUS PROTOCOL
The following defines the features of the I
2
C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05/09/17
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
24WC03
24WC05
24WC09
24WC17
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
A2
A2
A2
a10
A1
A1
a9
a9
A0
a8
a8
a8
R/W
R/W
R/W
R/W
* A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8, a9 and a10 correspond to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
5
Doc. No. 25063-00 2/98 S-1
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
