MICRONAS
DA9138/40.002
November 1, 1997
MAS9138/40
ASYNCHRONOUS TO SYNCHRONOUS CONVERTER
•
Pin compatible with MAS7838
•
Interfaces a duplex asynchronous to synchronous channel
•
Modem speeds of 600, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, 12k, 14.4k,
19.2k and 38.4k bps with a single 4.9152 MHz crystal
DESCRIPTION
MAS9138 is a single chip duplex asynchronous to
synchronous converter. It converts asynchronous start
stop characters to synchronous format, with stop bit
deletion when required as defined in the CCITT
recommendation V.14. On the receiver channel
MAS9138 converts the incoming synchronous data to
asynchronous start stop character format with stop bit
insertion when required as defined in the CCITT
recommendation V.14. MAS9138 implements the data
modes for the synchronous interface as specified in
the V.14. MAS9138 can be configured to operate at
any frequency up to 38.4 kbits/s within these modes.
The device contains a bit generator and frequency
selection logic to allow easy operation at other data
rates. With just one crystal the device can adapt to ten
(10) different bit rates so it is ideally suited to be used
with the most common modem systems ranging from
V.22 to V.34.
FEATURES
•
•
•
•
•
•
•
•
•
Implements CCITT recommendation V.14
Bypass operation
Character length from 8 to 11 bits including start
stop and parity bits
CMOS and LS-TTL compatible interface
Low power consumption (typically 10 mW)
No additional circuitry needed to perform
conversion
Single +3.3...+5V supply
Operating temperature -40
o
C to 85
o
C
16-pin PDIP and SO package
APPLICATION
•
•
•
•
Data communication systems
Adapts asynchronous terminals to synchronous
modems
Full or half card PC modems using UART as a data
source
Simplifying data multiplexing systems
BLOCK DIAGRAM
CL1
CONTROL
VDD
CL1
CONTROL
VDD
CL2
XSER
TMG
OSC
TSL
TXC
TDO
RXC
RDI
XASY
_
>
1
SYNC
TO
ASYNC
ASYNC
TO
SYNC
O
S
C
CL2
XSER
TMG
OSC
TSL
XTXC
TDI
TDO
XRXC
RDO
RDI
XASY
_
>
1
SYNC
TO
ASYNC
ASYNC
TO
SYNC
O
S
C
TDI
RDO
XHST
VSS
XHST
VSS
MAS9138
MAS9140
1
MICRONAS
PIN CONFIGURATION
PDIP 16
SO16
DA9138/40.002
November 1, 1997
MAS9138/40N
TSL 1
TMG 2
OSC 3
TXC* 4
CL1 5
CL2 6
XESR 7
VSS 8
16 VDD
15 RXC*
14 RDI
13 RDO
12 XHST
11 XASY
10 TDO
9 TDI
TSL 1
TMG 2
OSC 3
TXC* 4
CL1 5
CL2 6
XESR 7
VSS 8
MAS9138/40S
16
15
14
13
12
11
10
9
VDD
RXC*
RDI
RDO
XHST
XASY
TDO
TDI
* XTXC, XRXC for MAS9140N
* XTXC, XRXC for MAS9140S
PIN DESCRIPTION
Pin name
TSL
TMG
Pin no.
PDIP
SO
1
1
2
2
I/O
I
I
Function
Timing select. 0 selects external sampling timing 16 x TXC from pin
2, TMG. 1 selects internal sampling timing.
Timing. Square wave timing signal 16 x TXC (TSL = 0) or 128 x
TXCmax (TSL = 1).
Max f = 10 Mhz when VDD = 5v and 5MHz when VDD = 3.3v.
Oscillator. Output for crystal. If used, the crystal is connected between
pins 2 and 3.
Transmitter timing (MAS9138 only).
Synchronous square wave timing for transmitter. The transmitted data
output, TDO is synchronized to the rising edge of TXC. The duty cycle
of TXC has to be 50% +/- 5%.
Inverted transmitter timing (MAS9140 only).
Synchronous square wave timing for transmitter. The transmitted data
output, TDO is synchronized to the falling edge of XTXC. The duty
cycle of XTXC has to be 50% +/- 5%.
Character length. The total character length including one start bit,
one stop bit and possible parity bit is selected with the CL1 and CL2
signals.
Extended signalling rate. The tolerance of the synchronous bit rate
can be:
XESR = 1 (basic signalling rate) TXC -2.5%...+1.0%
XESR = 0 (extended signalling rate) TXC -2.5%...2.3%
Ground
OSC
TXC
3
4
3
4
O
I
XTXC
I
CL1
5
5
I
CL2
XESR
6
7
6
7
I
I
VSS
8
8
G
2
MICRONAS
PIN DESCRIPTION
Pin name
TDI
TDO
XASY
Pin no.
PDIP
9
10
11
SO
9
10
11
I/O
I
O
I
Function
DA9138/40.002
November 1, 1997
Transmitter data input. 1 = mark or stop bit. 0 = space, start or break
signal.
Transmitter data output. Output data is synchronized to the
synchronous timing signal TXC (pin 4). 1 = mark. 0 = space.
Asynchronous mode. XASY = 0 Asynchronous transmission, XASY =
1 Synchronous transmission. In synchronous transmission the
converter is totally bypassed in both directions: TDI = TDO, RDI =
RDO
Higher speed signalling timing. XHST = 1 normal synchronous to
asynchronous conversion (CCITT V.14). XHST = 0 asynchronous to
synchronous conversion with higher speed synchronous timing (TXC,
RXC). TXC and RXC timing must be 1-2% higher than the normal bit
rate in order to allow some overspeed in the asynchronous data.
On the receiver side the RX buffer is deleted and the synchronous
data RDI is directly connected to the asynchronous output RDO.
Receiver data output. RDO is the received data converted back to
asynchrnous mode.
1 = mark or stop bit, 0 = space, start or break signal
Receiver data input. 1 = mark, 0 = space. The received data must be
synchronized to the receiver timing RXC from the synchronous
channel (pin 15).
Receiver timing (MAS9138 only). Receiver square wave timing from
the synchronous channel. The received data RDI must be
synchronized to the rising edge of RXC.
Receiver timing (MAS9140 only). Receiver square wave timing from
the synchronous channel. The received data RDI must be
synchronized to the rising edge of XRXC.
Timings between synchronous clocks and data are shown on page
five. Note that absolute delays depend on the speed of data
transmission.
Power supply
XHST
12
12
I
RDO
13
13
O
RDI
14
14
I
RXC
15
15
I
XRXC
I
VDD
16
16
P
3
MICRONAS
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Storage Temperature
Symbol
VDD
Ts
Conditions
Min
-0.5
-55
DA9138/40.002
November 1, 1997
(GND = 0V)
Max
5.5
+150
Unit
V
o
C
RECOMMEDED OPERATION CONDITIONS
Parameter
Supply Voltage
Supply current
Operating Temperature
Symbol
VDD
IDD
Ta
VDD = 5V
Conditions
Min
3
2
-40
Typ
3.3 to
5.0
Max
5.25
5
+85
Unit
V
mA
o
C
ELECTRICAL CHARACTERISTICS
Inputs
(test conditions: -40 C to 85 C)
o
o
Parameter
Input low voltage
Input high voltage
Input leakage current
Input capacitance load
Internal pull-up resistor for
digital inputs
Symbol
V
IL
V
IH
I
IL
C
I
R
pull-up
Conditions
VDD=5V, VSS=0V
VDD=3.3V, VSS=0V
VDD=5V, VSS=0V
VDD=3.3V, VSS=0V
VDD=5V, VSS=0V
VDD=3.3V, VSS=0V
VDD=5V, VSS=0V
VDD=3.3V, VSS=0V
VDD=5V, VSS=0V, VIN=0.4V
VDD=5V, VSS=0V, VIN=2.5V
VDD=3.3V, VSS=0V,
VIN=0.4V
VDD=3.3V, VSS=0V,
VIN=1.5V
Min
Typ
Max
0.8
0.4
Unit
V
V
V
V
µA
µA
pF
pF
kΩ
kΩ
2
1.4
-100
-100
1
1
150
300
200
600
275
1000
350
1500
kΩ
kΩ
4
MICRONAS
ELECTRICAL CHARACTERISTICS
Outputs (TDO, RDO)
DA9138/40.002
November 1, 1997
(test conditions: -40 C to 85 C)
o
o
Parameter
Output low voltage
Symbol
V
OL
Conditions
VDD=5V, VSS=0V, I
OL
=+1.8mA
VDD=3.3V, VSS=0V,
I
OL
=+0.6mA
VDD=5V, VSS=0V, I
OL
=-4.3mA
VDD=3.3V, VSS=0V, I
OL
=-
2.1mA
Min
Typ
Max
0.4
0.2
Unit
V
V
V
V
Output high voltage
V
OH
3.0
1.8
Outputs (OSC)
(test conditions: -40 C to 85 C)
o
o
Parameter
Output low voltage
Symbol
V
OL
Conditions
VDD=5V, VSS=0V, I
OL
=+0.5mA
VDD=3.3V, VSS=0V,
I
OL
=+0.19mA
VDD=5V, VSS=0V, I
OL
=-1.4mA
VDD=3.3V, VSS=0V, I
OL
=-
0.7mA
Min
Typ
Max
0.4
0.2
Unit
V
V
V
Output high voltage
V
OH
3.0
1.8
Data timing
(test conditions:VDD=3.3V - 5V, VSS=0V, -40 C to 85 C)
o
o
Parameter
Low to high logic transition
time
High to low logic transition
time
Symbol
t
R
t
R
Conditions
CL = 10pF
CL = 10 pF
Min
Typ
20
20
Max
Unit
ns
ns
(test conditions:VDD=3.3V - 5V, VSS=0V, -40 C to 85 C, TSL = 1)
o
o
Parameter
TDO delay time after TXC
RDI setup time before RXC
RDI hold time after RXC
Symbol
T1
T2
T3
Conditions
Min
50
1/4
T
RXC
1/4
T
RXC
o
Typ
Max
T
TXC
/16
+ 350
Unit
ns
ns
ns
(test conditions:VDD=3.3V - 5V, VSS=0V, -40 C to 85 C, TSL = 0, TMG = 16xTXC)
o
Parameter
TDO delay time after TXC
RDI setup time before RXC
RDI hold time after RXC
Symbol
T1
T2
T3
Conditions
Min
50
1/4
T
RXC
1/4
T
RXC
Typ
Max
1/TMG
+ 350
Unit
ns
ns
ns
5
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