DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
ENHANCED MULTIFORMAT, DELTA-SIGMA,
AUDIO DIGITAL-TO-ANALOG CONVERTER
FEATURES
D
Supports DSD and PCM Format
D
Accepts 16-, 18-, 20- and 24-Bit Audio Data for
D
D
PCM Format
Accepts Direct Stream Digital (1 bit)
Analog Performance (V
CC
= 5 V):
– Dynamic Range: 106 dB Typ
– SNR: 106 dB Typ
– THD+N: 0.0015% Typ
– Full–Scale Output: 3.1 V(pp) Typ
Includes 8x Oversampling Digital Filter for
PCM Format:
– Stopband Attenuation: –60 dB
– Passband Ripple:
±0.02
dB
Including Digital DSD Filter For DSD Format:
– Passband Choices: 50 kHz, 70 kHz or
60 kHz at
–3
dB
Sampling Frequency:
– PCM Mode: 10 kHz to 200 kHz
– DSD Mode: 64
×
44.1 kHz
System Clock:
– 128f
s
192f
s
, 256f
s
, 384f
s
512f
s
, 768f
s
Data Formats:
– Standard, I
2
S, and Left-Justified for PCM
Direct Stream Digital
User-Programmable Mode Controls:
– Digital Attenuation
– Digital De-Emphasis
– Digital Filter Roll-Off: Sharp or Slow Soft
Mute
– Zero Detect Mute
– Zero Flags for Each Output
D
Dual Supply Operation:
D
D
5-V Analog, 3.3-V Digital
5-V Tolerant Digital Inputs
Small 20-Lead QSOP Package
D
APPLICATIONS
D
Universal A/V Players
D
SACD Players
D
Car Audio Systems
D
Other Applications Requiring 24-Bit Audio
DESCRIPTION
The DSD1702 is a CMOS, monolithic, stereo
digital-to-analog converter that supports both PCM
audio data format and direct stream digital (DSD) audio
data format.
The device includes an 8x digital interpolation filter for
PCM signals. A digital DSD filter provides three different
selectable frequency response options, followed by
Burr-Brown’s enhanced multilevel delta-sigma
modulator employing 4th-order noise shaping and
8-level amplitude quantization. This design achieves
excellent dynamic performance and improved
tolerance to clock jitter.
DSD1702 sampling rates of up to 192 kHz for PCM
mode and 44.1 kHz
×
64 for DSD mode are supported.
A full set of user-programmable functions is accessible
through a 3-wire serial control port, supporting register
write functions.
The DSD1702 is available in a 20-lead QSOP package.
D
D
D
D
D
This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate
precaustions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2002, Texas Instruments Incorporated
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1
DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
DSD1702
(TOP VIEW)
DSDL
DSDR
PBCK
PDATA
PLRCK
DGND
V
DD
V
CC
V
OUT
L
V
OUT
R
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DBCK
DSCK
PSCK
MS
MC
MD
ZEROL/NA
ZEROR/ZEROA
V
COM
AGND
PACKAGE/ORDERING INFORMATION
PRODUCT
DSD1702E
PACKAGE
QSOP 20
QSOP–20
PACKAGE
DRAWING NUMBER
4073301
OPERATION
TEMPERATURE RANGE
25°C
–25°C to 85°C
PACKAGE
MARKING
DSD1702E
ORDERING
NUMBER†
DSD1702E
TRANSPORT
MEDIA
Rails
DSD1702E/2K
Tape and Reel
† Models with a slash (/) are available only in tape and reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000
pieces of DSD1702E/2K will get a single 2000-piece tape and reel.
block diagram
PLRCK
PBCK
PDATA
PSCK
DSCK
DBCK
DSDL
DSDR
MS
MC
MD
Mode
Control
Power Control
DSD
I/F
DSD
Filter
PCM
I/F
PCM
Filter
(×8 DF)
Multilevel
Delta-Sigma
Modulator
ZEROL
ZEROR/ZEROA
M
U
X
M
U
X
Multilevel
DAC
Analog
LPF
VOUTL
VOUTR
VCOM
VCC
DGND AGND VDD
2
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
Terminal Functions
TERMINAL
NAME
DSDL
DSDR
PBCK
PDATA
PLRCK
DGND
VDD
VCC
VOUTL
VOUTR
AGND
VCOM
ZEROR/ZEROA
ZEROL/NA
MD
MC
MS
PSCK
DSCK
DBCK
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O
I
I
I
I
I
–
–
–
O
O
–
–
O
O
I
I
I
I
I
I
DESCRIPTIONS
Audio data digital input (DSD L–channel) (see Note 1)
Audio data digital input (DSD R–channel) (see Note 1)
Audio data bit clock input. (PCM) (see Note 1)
Audio data digital input. (PCM) (see Note 1)
Audio data latch enable input. (PCM) (see Note 1)
Digital ground
Digital power supply, 3.3 V
Analog power supply, 5 V
Analog output for L–channel
Analog output for R–channel
Analog ground
Common voltage decoupling
Zero flag output for R–channel/zero flag output for L/R–channel. (see Note 3)
Zero flag output for L–channel/no assignment (see Note 3)
Mode control data Input. (see Note 2)
Mode control clock input. (see Note 2)
Chip Select for Mode control. (see Note 2)
System clock input. (PCM) (see Note 1)
System clock input. (DSD) (see Note 1)
Audio data bit clock input. (DSD) (see Note 1)
NOTES: 1. Schmitt trigger input, 5-V tolerant.
2. Schmitt trigger input with internal pulldown, 5-V tolerant.
3. Usage depending on AZRO register setting.
absolute maximum ratings
†
Supply voltage, V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Supply voltage, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 V
Ground voltage differences, AGND, DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±0.1
V
Digital input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (6.5 V + 0.3 V)
Input current (Any pins except supplies) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±10
mA
Ambient temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead temperature (soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C, 5 sec
Package temperature (IR reflow, peak) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C, 10 sec
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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3
DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
electrical characteristics, T
A
= 25°C, V
DD
= 3.3 V, V
CC
= 5 V (unless otherwise noted)
In PCM mode, f
S
= 44.1 kHz, system clock = 256 f
S
, 24-bit data
In DSD mode, f
S
= 2.8224 MHz (= 64
×
44.1 kHz), system clock = 256
×
44.1 kHz, 1-bit data
DSD1702E
PARAMETERS
Resolution
DATA FORMAT
PCM MODE
Audio data interface format
Audio data bit length
Audio data format
fs
Sampling frequency
System clock frequency
DSD MODE
Audio data interface format
Audio data bit length
fs
Sampling frequency
System clock frequency
Digital Input/OUTPUT
Logic Family
VIH
VIL
IIH(4)
IIL(4)
IIH(5)
IIL(5)
VOH (6)
VOL (6)
2.0
Input logic level
VIN = VDD
VIN = 0 V
VIN = VDD
VIN = 0 V
IOH = –2 mA
IOL = 2 mA
2.4
1.0
VDC
65
0.8
10
–10
100
–10
µA
A
VDC
TTL Compatible
fs = 44.1 kHz
fs = 44.1 kHz
Direct stream digital (DSD)
1-Bit
64fs
256fs, 384fs, 512fs, 768fs
Hz
kHz
Standard, I2S, left justified
16-, 18-, 20-, 24-bits
selectable
MSB First, 2s Complement
10
200
kHz
128fs, 192fs, 256fs, 384fs,
512fs, 768fs
TEST CONDITIONS
MIN
TYP
24
MAX
UNITS
Bits
Input logic current
Output logic level
NOTES: 4. Pins 1, 2, 3, 4, 5, 18, 19, 20: DSDL, DSDR, PBCK, PDATA, PLRCK, PSCK, DSCK, DBCK.
5. Pins 15, 16, 17: MD, MC, MS.
6. Pins 13, 14: ZEROR, ZEROL.
4
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DSD1702
SLES005A – JUNE 2001 – REVISED FEBRUARY 2002
electrical characteristics, T
A
= 25°C, V
DD
= 3.3 V, V
CC
= 5 V (unless otherwise noted) (continued)
In PCM mode, f
s
= 44.1 kHz, system clock = 256f
s
, 24-bit data
In DSD mode, f
s
= 2.8224 MHz (= 64
×
44.1 kHz), system clock = 256
×
44.1 kHz, 1-bit data
DSD1702E
PARAMETERS
Dynamic Performance(7)
PCM MODE
fs = 44.1 kHz
fs = 96 kHz
fs = 192 kHz
EIAJ, A-Weighted,
Dynamic range
A-Weighted,
fs = 192 kHz
EIAJ, A-Weighted,
( )
Signal-to-noise ratio(8)
Signal to noise
A-Weighted,
fs = 192 kHz
fs = 44.1 kHz
Channel se aration
separation
Level linearity error
DSD MODE
(at fs = 64
×
44.1 kHz)
THD+N
Dynamic range
Signal–to–noise ratio
Channel separation
Level linearity error
DC Accuracy
Gain error
Gain mismatch, channel-to-channel
Bipolar zero error
Analog Output
Output voltage
Center voltage
Load impedance
Digital Filter Performance
8x Interpolation Filter
Sharp roll off Filter
Passband
Passband
Stopband
Passband ripple
Stopband Attenuation
Stopband = 0.546fs
– 60
NOTES: 7. Analog performance specs are measured by audio precision system 2 under averaging mode.
8. SNR is tested at infinite zero detection OFF.
±0.02
dB
–3 dB
0.546fs
±
0.02
dB
dB
0.454fs
0.487fs
AC load
5
Full scale (–0dB)
62%/VCC
50%/VCC
V(PP)
VDC
kΩ
VOUT = 0.5 VCC at BPZ
±1.0
±1.0
±30
±6.0
±3.0
±60
%/FSR
%/FSR
mV
VOUT =
–90
dB
VOUT = 0 dB, EIAJ
EIAJ, A-Weighted
EIAJ, A-Weighted
0.0015%
106
106
103
±0.5
dB
dB
dB
dB
fs = 96 kHz
fs = 192 kHz
VOUT = –90 dB
fs = 44.1 kHz
fs = 96 kHz
fs = 44.1 kHz
fs = 96 kHz
103
0.0015%
0.0020%
0.0025%
106
106
105
103
106
106
105
100
103
103
102
±0.5
dB
dB
dB
dB
0.002%
TEST CONDITIONS
MIN
TYP
MAX
UNITS
THD+N at VOUT = 0 dB
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