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CD4086BFMSR

产品描述4000/14000/40000 SERIES, 8-INPUT AND-OR-INVERT GATE, CDIP14, FRIT SEALED, DIP-14
产品类别逻辑    逻辑   
文件大小86KB,共9页
制造商Intersil ( Renesas )
官网地址http://www.intersil.com/cda/home/
下载文档 详细参数 全文预览

CD4086BFMSR概述

4000/14000/40000 SERIES, 8-INPUT AND-OR-INVERT GATE, CDIP14, FRIT SEALED, DIP-14

CD4086BFMSR规格参数

参数名称属性值
是否Rohs认证不符合
Objectid1531371144
零件包装代码DIP
包装说明DIP, DIP14,.3
针数14
Reach Compliance Codenot_compliant
系列4000/14000/40000
JESD-30 代码R-GDIP-T14
JESD-609代码e0
长度19.43 mm
负载电容(CL)50 pF
逻辑集成电路类型AND-OR-INVERT GATE
最大I(ol)0.00036 A
功能数量1
输入次数8
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
封装主体材料CERAMIC, GLASS-SEALED
封装代码DIP
封装等效代码DIP14,.3
封装形状RECTANGULAR
封装形式IN-LINE
电源5/15 V
Prop。Delay @ Nom-Sup837 ns
传播延迟(tpd)837 ns
认证状态Not Qualified
施密特触发器NO
筛选级别MIL-PRF-38535 Class V
座面最大高度1.2 mm
标称供电电压 (Vsup)5 V
表面贴装NO
技术CMOS
温度等级MILITARY
端子面层TIN LEAD
端子形式THROUGH-HOLE
端子节距2.54 mm
端子位置DUAL
总剂量100k Rad(Si) V
宽度7.62 mm

文档预览

下载PDF文档
CD4086BMS
December 1992
CMOS Expandable 4-Wide 2-Input
AND-OR-INVERT Gate
Pinout
CD4086BMS
TOP VIEW
Features
• Medium Speed Operation - tPHL = 90ns; tPLH = 140ns
(Typ.) at 10V
• High Voltage Type (20V Rating)
• INHIBIT and ENABLE Inputs
• Buffered Outputs
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• Standardized Symmetrical Output Characteristics
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
A 1
B 2
J = INH + ENABLE +
AB + CD + EF + GH 3
NC 4
E 5
F 6
VSS 7
14 VDD
13 D
12 C
11 ENABLE/EXP
10 INHIBIT/EXP
9 H
8 G
NC = NO CONNECTION
Functional Diagram
10 INHIBIT/EXP
Description
CD4086BMS contains one 4-wide 2-input AND-OR-INVERT
gate with an INHIBIT/EXP input and an ENABLE/EXP input.
For a 4-wide A-O-I function INHIBIT/EXP is tied to VSS and
ENABLE/EXP to VDD. See Figure 2 and its associated
explanation for applications where a capability greater than
4-wide is required.
The CD4076B is supplied in these 14 lead outline packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4H
H1B
H4F
G
H
A
B
1
2
C
D
E
F
12
13
3
J
5
6
LOGIC 1
HIGH
LOGIC 0
LOW
VDD = 14
VSS = 7
NC = 4
8
9
11 ENABLE/EXP
J = INH + ENABLE + AB + CD + EF + GH
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
File Number
3328
7-1055

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