MSM832 - 12/15
ISSUE 4.2 : November 1998
32K x 8 SRAM
MSM832 - 12/15
11403 West Bernado Court, Suite 100, San Diego, CA 92127.
Tel No: (619) 674 2233, Fax No: (619) 674 2230
Issue 4.2 : November 1998
Description
The MSM832 is a Static RAM organised as 32K x
8 available with access times of 120 or 150 ns.
The device is available in five ceramic package
options including the high denisty VIL™ package.
It features completely static operation with a low
power standby mode and is 3.0V battery back-up
compatible. It is directly TTL compatible and has
common data inputs and outputs.
The device may be screened in accordance with
MIL-STD-883.
32,768 x 8 CMOS Static RAM
Features
• Access Times of 120/150 ns.
• JEDEC Standard footprint.
• Low Power Operation : 385 mW (max)
• Low Power Standby : 1.1 mW (max) -L version.
• Low Voltage Data Retention.
• Directly TTL compatible.
• Completely Static Operation.
Block Diagram
Pin Definitions
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
1
2
3
4
5
6 TOP VIEW
7 PACKAGE
8
V,T,S
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
W
E
A13
A8
A9
A11
OE
A10
CS
D7
D6
D5
D4
D3
A3
A4
A5
A6
A7
A8
A12
A13
A14
X
Address
Buffer
Row
Decoder
Memory Array
512 X 512
D0
D7
I/O
Buffer
Column I/O
Column Decoder
WE
OE
Y Address Buffer
A6
A5
A4
A3
A2
A1
A0
NC
D0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A7
A12
A14
NC
Vcc
WE
A13
CS
J,W
PACKAGE
TOP VIEW
A8
A9
A11
NC
OE
A10
CS
D7
D6
A0
A1
A2
A9
A10
A11
20
19
18
17
16
15
14
D5
D4
D3
NC
GND
D2
D1
Package Details
Pin Count
28
28
28
32
32
Description
Package Type
V
T
S
J
W
0.1" Vertical-in-Line (VIL
TM
)
0.3" Dual-in-line (SKINNY DIP)
0.6"Dual-in-Line (DIP)
J-Leaded Chip Carrier (JLCC)
Leadless Chip Carrier (LCC)
Pin Functions
A0-A14
Address inputs
D0-7
Data Input/Output
CS
Chip Select
OE
Output Enable
WE
Write Enable
V
CC
Power(+5V)
GND
Ground
1
ISSUE 4.2 : November 1998
MSM832 - 12/15
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Voltage on any pin relative to V
SS (2)
Power Dissipation
Storage Temperature
V
T
P
T
T
STG
-0.5V to +7
1
-65 to +150
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
(2) Pulse width:- -3.0V for less than 50ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AL
T
AM
min
4.5
2.2
-0.5
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
V
CC
+0.5
0.8
70
85
125
Unit
V
V
V
o
o
C
C ( Suffix
I
)
C ( Suffix
M, MB
)
o
DC Electrical Characteristics
(V
CC
= 5.0V±10%, T
A
=-55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Average Supply Current
Standby Supply Current
Symbol Test Condition
I
LI
I
LO
I
CC
I
SB1
I
SB2
V
OL
V
OH
V
IN
=0V to V
CC
CS=V
IH
or OE=V
IH
,V
I/O
= V
SS
to V
CC
,WE=V
IL
CS=V
IL
,I
I/O
=0mA, Min. Cycle, Duty=100%
CS=V
IH
,Min Cycle.
CS≥V
CC
-0.2V, 0.2V≥V
IN
≥V
CC
-0.2V
I
OL
= 2.1 mA
I
OH
= -1.0 mA
min
-
-
-
-
-
-
2.4
typ
-
-
-
-
-
-
-
max
2
2
70
3
200
0.4
-
Unit
µA
µA
mA
mA
mA
V
V
-L Version
Output Voltage
Typical values at V
CC
=5.0V,T
A
=25
O
C and specified loading
Capacitance
(V
CC
=5V±10%,T
A
=25°C)
Parameter
Input Capacitance
I/O Capacitance
Note:
Symbol Test Condition
C
IN
C
I/O
V
IN
= 0V
V
I/O
= 0V
min
-
-
typ
-
-
max
8
10
Unit
pF
pF
This parameter is not 100% tested.
2
MSM832 - 12/15
ISSUE 4.2 : November 1998
Operating Modes
The table below shows the logic inputs required to control the MSM832.
Mode
Not Selected
OutputDisable
Read
Write
CS
1
0
0
0
OE
X
1
0
X
1 = V
IH
,
WE
X
1
1
0
V
CC
Current
I
SB1
,I
SB2
I
CC
I
CC
I
CC
0 = V
IL
,
I/O Pin Reference Cycle
High Z
High Z
D
OUT
D
IN
Read Cycle
Write Cycle
Power Down
X = Don't Care
Low V
cc
Data Retention Characteristics - L Version Only
( T
A
=-55°C to +125°C)
Parameter
V
CC
for Data Retention
Data Retention Current -L Version
Chip Deselect to Data Retention Time
Operation Recovery Time
Notes (1) t
RC
= Read Cycle Time
Symbol
V
DR
I
CCDR2
t
CDR
t
R
Test Condition
CS≥V
CC
-0.2V, V
IN
≥0V
See Retention Waveform
See Retention Waveform
min
2.0
0
t
RC(1)
typ
-
-
-
-
max
-
170
-
-
Unit
V
µA
ns
ns
V
CC
=3.0V, CS≥V
CC
-0.2V, V
IN
≥0V
-
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
cc
=5V±10%
Output Load
I/O Pin
166
Ω
1.76V
30pF
3
ISSUE 4.2 : November 1998
MSM832 - 12/15
AC OPERATING CONDITIONS
Read Cycle
12
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z
(3)
Output Disable to Output in High Z
(3)
15
max
-
120
120
60
-
-
-
40
40
Symbol min
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
120
-
-
-
10
10
5
0
0
min
150
-
-
-
10
10
5
0
0
max
-
150
150
70
-
-
-
50
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
(3)
Output Active from End of Write
12
Symbol min. max
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
120
85
85
0
70
0
0
50
0
-
5
-
-
-
-
-
-
40
-
-
40
-
15
min.
150
100
100
0
90
0
0
60
0
-
5
max
-
-
-
-
-
-
50
-
-
50
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
MSM832 - 12/15
ISSUE 4.2 : November 1998
Read Cycle Timing Waveform
(1)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
CLZ
t
ACS
t
CHZ(3)
t
OHZ(3)
Dout
High-Z
Data Valid
Notes :
(1) During the Read Cycle, WE is High.
(2) Address valid prior to or coincident with CS transition low.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs acheive the open circuit conditions and are not
referenced to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t
WC
Address
t
AS(3)
t
AW
t
CW(4)
(6)
OE
t
WR
(2)
CS
t
WP(1)
WE
t
OHZ(3,9)
High-Z
t
DW
High-Z
t
OW
t
DH
Dout
Din
Data Valid
5
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