Table of Contents
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 6
Chapter 2. Functional Description ........................................................................................................ 7
General Description .............................................................................................................................................. 7
Convolutional Encoding ............................................................................................................................... 7
Punctured Codes ......................................................................................................................................... 8
Continuous and Block Encoding .................................................................................................................. 9
Zero Flushing and Tail Biting Termination Modes........................................................................................ 9
Functional Description........................................................................................................................................... 9
Encoder........................................................................................................................................................ 9
Puncture Unit ............................................................................................................................................. 10
Input Memory ............................................................................................................................................. 10
Control Unit ................................................................................................................................................ 10
Interfacing to the Block Convolutional Encoder Core.......................................................................................... 10
Signal Descriptions ............................................................................................................................................. 11
Timing Diagrams ................................................................................................................................................. 12
Chapter 3. Parameter Settings ............................................................................................................ 19
Block Convolutional Encoder Parameters........................................................................................................... 20
Code Rate .................................................................................................................................................. 20
Operation Mode ......................................................................................................................................... 21
Puncture Support ....................................................................................................................................... 21
Termination Mode ...................................................................................................................................... 21
Block Length Options ................................................................................................................................. 21
Generator Polynomials............................................................................................................................... 21
Chapter 4. IP Core Generation............................................................................................................. 22
Licensing the IP Core.......................................................................................................................................... 22
Getting Started .................................................................................................................................................... 22
IPexpress-Created Files and Top Level Directory Structure............................................................................... 25
Instantiating the Core .......................................................................................................................................... 26
Running Functional Simulation ........................................................................................................................... 26
Synthesizing and Implementing the Core in a Top-Level Design ....................................................................... 27
Hardware Evaluation........................................................................................................................................... 28
Enabling Hardware Evaluation in Diamond:............................................................................................... 28
Enabling Hardware Evaluation in ispLEVER:............................................................................................. 28
Updating/Regenerating the IP Core .................................................................................................................... 28
Regenerating an IP Core in Diamond ........................................................................................................ 28
Regenerating an IP Core in ispLEVER ...................................................................................................... 29
Chapter 5. Support Resources ............................................................................................................ 30
Lattice Technical Support.................................................................................................................................... 30
Online Forums............................................................................................................................................ 30
Telephone Support Hotline ........................................................................................................................ 30
E-mail Support ........................................................................................................................................... 30
Local Support ............................................................................................................................................. 30
Internet ....................................................................................................................................................... 30
References.......................................................................................................................................................... 30
LatticeEC/ECP ........................................................................................................................................... 30
LatticeECP2M ............................................................................................................................................ 30
LatticeECP3 ............................................................................................................................................... 31
© 2010 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG31_03.5, June 2010
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Block Convolutional Encoder User’s Guide
Lattice Semiconductor
Table of Contents
LatticeSC/M................................................................................................................................................ 31
LatticeXP.................................................................................................................................................... 31
LatticeXP2.................................................................................................................................................. 31
Revision History .................................................................................................................................................. 31
Appendix A. Resource Utilization ....................................................................................................... 32
LatticeECP and LatticeEC FPGAs ...................................................................................................................... 32
Ordering Part Number................................................................................................................................ 32
LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 33
Ordering Part Number................................................................................................................................ 33
LatticeECP2M FPGAs......................................................................................................................................... 33
Ordering Part Number................................................................................................................................ 33
LatticeECP3 FPGAs............................................................................................................................................ 34
Ordering Part Number................................................................................................................................ 34
LatticeXP FPGAs ................................................................................................................................................ 34
Ordering Part Number................................................................................................................................ 34
LatticeXP2 FPGAs .............................................................................................................................................. 35
Ordering Part Number................................................................................................................................ 35
LatticeSC and LatticeSCM FPGAs ..................................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
IPUG31_03.5, June 2010
3
Block Convolutional Encoder User’s Guide
Chapter 1:
Introduction
Lattice’s Block Convolutional Encoder IP core is a parameterizable core for convolutional encoding of continuous or
burst input data streams. The core allows different code rates and constraint lengths and supports puncturing. It
can operate in continuous or block mode, whichever is required by the channel. In block mode, either Zero Flushing
or Tail Biting codes can be generated. All the configurable parameters, including operation mode, termination
mode, generator polynomials, code rate, and puncture pattern, can be defined by the user to suit the needs of the
application. The code rate and the puncture pattern can also be varied through the input ports dynamically, provid-
ing further flexibility for the IP usage. Lattice’s Block Convolutional Encoder IP core is compatible with many net-
working and wireless standards that use convolutional encoding.
Quick Facts
Table 1-1
through
Table 1-4
give quick facts about the Block Convolutional Encoder IP core for LatticeEC™,
LatticeECP™, LatticeECP2™, LatticeECP2M™, LatticeECP3™, LatticeXP™, LatticeXP2™, LattticeSC™, and
LatticeSCM™ devices.
Table 1-1. Block Convolutional Encoder IP Core for LatticeEC/ECP/XP Devices Quick Facts
Block Convolutional Encoder IP Configuration
Puncture
Rate 2/3
Constraints 3
Block
802.16- 2004
SC PHY
Non-punc-
ture Rate 1/2
Constraints 9
Block
3GPP/
CDMA2000
Non-punc-
ture Rate 1/2
Constraints 7
Continuous
802.11a, also
DVB-S
Dynamic
puncture
Max rate 5/6
Constraints 7
Block
802.16-2004
OFDM PHY
Puncture
Rate 3/4
Constraints 7
Continuous
802.11a, also
DVB-S
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Lattice EC/ECP/XP
LFEC1E/LFECP6E/LFXP3E
LFEC20E-5F672C/LFECP20E-5F672C/LFXP20E-5F484C
50
50
50
0
50
50
50
150
100
150
50
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Diamond
®
1.0 or ispLEVER
®
8.1
Synopsys
®
Synplify
®
Pro for Lattice D-2009.12L-1
Aldec
®
Active-HDL
®
8.2 Lattice Edition
Mentor Graphics
®
ModelSim
®
SE 6.3F
Design Tool
Support
Synthesis
Simulation
IPUG31_03.5, June 2010
4
Block Convolutional Encoder User’s Guide
Lattice Semiconductor
Introduction
Table 1-2. Block Convolutional Encoder IP Core for LatticeECp2/ECP2M/XP2 Devices Quick Facts
Block Convolutional Encoder IP Configuration
Puncture
Rate 2/3
Constraints 3
Block
802.16- 2004
SC PHY
Non-punc-
ture Rate 1/2
Constraints 9
Block
3GPP/
CDMA2000
Non-punc-
ture Rate 1/2
Constraints 7
Continuous
802.11a, also
DVB-S
Dynamic
puncture
Max rate 5/6
Constraints 7
Block
802.16-2004
OFDM PHY
Puncture
Rate 3/4
Constraints 7
Continuous
802.11a, also
DVB-S
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Lattice ECP2/ECP2M/XP2
LFE2-6E/ LFE2M20E/ LFXP2-5E
LFE2-50E-7F672C/LFE2M35E-7F484C/LFXP2-17E-7F484C
50
50
50
0
50
50
50
150
100
150
50
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Design Tool
Support
Synthesis
Simulation
Table 1-3. Block Convolutional Encoder IP Core for LatticeSC/SCM Devices Quick Facts
Block Convolutional Encoder IP Configuration
Puncture
Rate 2/3
Constraints 3
Block
802.16- 2004
SC PHY
Non-punc-
ture Rate 1/2
Constraints 9
Block
3GPP/
CDMA2000
Non-punc-
ture Rate 1/2
Constraints 7
Continuous
802.11a, also
DVB-S
Dynamic
puncture
Max rate 5/6
Constraints 7
Block
802.16-2004
OFDM PHY
Puncture
Rate 3/4
Constraints 7
Continuous
802.11a, also
DVB-S
Core
Requirements
FPGA Families Supported
Minimal Device Needed
Targeted Device
Lattice SC/SCM
LFSC3GA15E/ LFSCM3GA15EP1
LFSC3GA25E-7F900C/ LFSCM3GA25EP1-7F900C
50
50
50
0
50
50
50
150
100
150
50
Resource
Utilization
LUTs
sysMEM EBRs
Registers
Lattice Implementation
Diamond 1.0 or ispLEVER 8.1
Synopsys Synplify Pro for Lattice D-2009.12L-1
Aldec Active-HDL 8.2 Lattice Edition
Mentor Graphics ModelSim SE 6.3F
Design Tool
Support
Synthesis
Simulation
IPUG31_03.5, June 2010
5
Block Convolutional Encoder User’s Guide
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