CAT1026, CAT1027
Dual Voltage Supervisory Circuits with I
2
C Serial 2k-bit CMOS EEPROM
FEATURES
■
Precision V
CC
power supply voltage monitor
■
Low power CMOS technology
■
16-Byte page write buffer
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
— 5V, 3.3 V and 3 V systems
— Five threshold voltage options
■
Additional voltage monitoring
■
Built-in inadvertent write protection
■
1,000,000 Program/Erase cycles
■
Manual reset capability
■
100 year data retention
■
8-pin DIP, SOIC, TSSOP, MSOP or TDFN
— Externally adjustable down to 1.25 V
■
Watchdog timer (CAT1027 only)
■
Active high or low reset
— Valid reset guaranteed to V
CC
= 1 V
■
400 kHz I
2
C bus
■
3.0 V to 5.5 V operation
(3 x 3 mm foot-print) packages
— TDFN max height is 0.8mm
■
Industrial and extended temperature ranges
DESCRIPTION
The CAT1026 and CAT1027 are complete memory and
supervisory solutions for microcontroller-based systems.
A 2k-bit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I
2
C bus.
The CAT1026 and CAT1027 provide a precision V
CC
sense circuit with five reset threshold voltage options
that support 5V, 3.3V and 3V systems. The power
supply monitor and reset circuit protects memory and
systems controllers during power up/down and against
brownout conditions. If power supply voltages are out of
tolerance reset signals become active preventing the
system microcontroller, ASIC, or peripherals from
operating.
used as an input for push-button manual reset capability.
The CAT1026 and CAT1027 provide an auxiliary voltage
sensor input, V
SENSE
, which is used to monitor a second
system supply. The auxiliary high impedance comparator
drives the open drain output, V
LOW
, whenever the sense
voltage is below 1.25V threshold.
The CAT1027 is designed with a 1.6 second watchdog timer
circuit that resets a system to a known state if software or a
hardware glitch halts or “hangs” the system. The CAT1027
features a watchdog timer interrupt input, WDI.
The on-chip 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided by a
V
CC
sense circuit that prevents writes to memory whenever
V
CC
falls below the reset threshold or until V
CC
reaches the
The CAT1026 features two open drain reset outputs: reset threshold during power up.
one (RESET) drives high and the other (RESET) drives Available packages include an 8-pin DIP, 8-pin SOIC, 8-
low whenever V
CC
falls below the threshold. Reset pin TSSOP, 8-pin TDFN and 8-pin MSOP. The TDFN
outputs become inactive typically 200 ms after the package thickness is 0.8mm maximum. TDFN footprint is
supply voltage exceeds the reset threshold value. With 3x3mm.
both active high and low reset signals, interface to
microcontrollers and other ICs is simple. CAT1027 has
only a
RESET
output. In addition, the
RESET
pin can be
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 3010, Rev. K
CAT1026, CAT1027
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
RESET Threshold Options
Part Dash Minimum Maximum
Number Threshold Threshold
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
SDA
START/STOP
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
VCC Monitor
VCC
HIGH VOLTAGE/
TIMING CONTROL
STATE COUNTERS
SCL
+
-
VREF
RESET
Controller
WDI
(CAT1027)
SLAVE
ADDRESS
COMPARATORS
Auxiliary Voltage Monitor
VSENSE
VREF
RESET
(CAT1026)
VLOW
RESET
+
-
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
TSSOP Package (U, Y)
MSOP Package (R, Z)
VLOW 1
RESET
2
VSENSE 3
VSS 4
CAT1026
8 VCC
7 RESET
6 SCL
5 SDA
(Bottom View)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (RD4, ZD4)
VCC
RESET
SCL
SDA
8
7
6
5
1
2
VLOW
RESET
VSENSE
VSS
CAT1026
3
4
VLOW 1
RESET
2
VSENSE 3
VSS 4
CAT1027
8 VCC
7 WDI
6 SCL
5 SDA
VCC
WDI
SCL
SDA
8
7
6
5
1
2
VLOW
RESET
VSENSE
VSS
CAT1027
3
4
Doc. No. 3010, Rev. K
2
CAT1026, CAT1027
PIN DESCRIPTION
RESET/RESET
RESET:
RESET OUTPUTS
RESET
(RESET CAT1026 Only)
These are open drain pins and
RESET
can be used as a
manual reset trigger input. By forcing a reset condition on
the pin the device will initiate and maintain a reset condition.
The RESET pin must be connected through a pull-down
resistor, and the
RESET
pin must be connected through a
pull-up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire-ORed with other open drain
or open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
V
SENSE
:
AUXILIARY VOLTAGE MONITOR INPUT
The V
SENSE
input is a second voltage monitor which
is compared against CAT1026 and CAT1027 internal
reference voltage of 1.25V typically. Whenever the
input voltage is lower than 1.25V, the open drain
VLOW output will be driven low. An external resistor
divider is used to set the voltage level to be sensed.
Connect V
SENSE
to V
CC
if unused.
V
LOW
:
AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when V
SENSE
is less
than 1.25V and goes high when V
SENSE
exceeds the
reference voltage.
WDI (CAT1027 Only):
WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low to
high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
PIN FUNCTIONS
Pin Name
RESET
V
SS
SDA
SCL
RESET
V
CC
V
SENSE
V
LOW
WDI
OPERATING TEMPERATURE RANGE
Industrial
Extended
-40˚C to 85˚C
-40˚C to 125˚C
Function
Active Low Reset Input/Output
Ground
Serial Data/Address
Clock Input
Active High Reset Output (CAT1026 only)
Power Supply
Auxiliary Voltage Monitor Input
Auxiliary Voltage Monitor Output
Watchdog Timer Interrupt (CAT1027 only)
CAT10XX FAMILY OVERVIEW
Device
Manual
Reset
Input Pin
Watchdog
Watchdog
Monitor
Pin
SDA
SDA
WDI
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET: Active
High and LOW
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
2k
2k
2k
2k
2k
2k
WDI
2k
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
3
Doc No. 3010, Rev. K
CAT1026, CAT1027
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to Ground
(1)
........... –2.0 V to V
CC
+ 2.0 V
V
CC
with Respect to Ground ............ –2.0 V to + 7.0 V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 seconds) ...... 300°C
Output Short Circuit Current
(2)
........................ 100 mA
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions outside of those listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for extended periods may affect device
performance and reliability.
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to
-2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is
V
CC
+0.5 V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a
time.
DC OPERATING CHARACTERISTICS
V
CC
= 3.0 V to 5.5 V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL(1)
V
IH(1)
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current
(Write)
Power Supply Current
(Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
(SDA,
RESET ,
V
LOW
)
Output High Voltage
(RESET)
I
OL
= 3 mA
V
CC
= 2.7 V
I
OH
= -0.4 mA
V
CC
= 2.7 V
CAT102x-45
(V
CC
= 5.0 V)
CAT102x-42
(V
CC
= 5.0 V)
V
TH
Reset Threshold
(V
CC
Monitor)
CAT102x-30
(V
CC
= 3.3 V)
CAT102x-28
(V
CC
= 3.3 V)
CAT102x-25
(V
CC
= 3.0 V)
V
RVALID
V
RT(2)
V
REF
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
Auxiliary Voltage Monitor
Threshold
Vcc -
0.75
4.50
4.25
3.00
2.85
2.55
1.00
15
1.2
1.25
1.3
4.75
4.50
3.15
3.00
2.70
V
mV
V
V
Test Conditions
V
IN
= GND to Vcc
V
IN
= GND to Vcc
f
SCL
= 400 kHz
V
CC
= 5.5 V
f
SCL
= 400 kHz
V
CC
= 5.5 V
Vcc = 5.5V
CAT1026
V
IN
= GND or Vcc CAT1027
-0.5
0.7 x Vcc
Min
-2
-10
Typ
Max
10
10
3
1
50
60
0.3 x Vcc
Vcc + 0.5
0.4
V
V
V
V
Units
µA
µA
mA
mA
µA
Notes:
1. V
IL
min and V
IH
max are reference values only and are not tested.
2. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. 3010, Rev. K
4
CAT1026, CAT1027
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
V
OUT
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
AC CHARACTERISTICS
V
CC
= 3.0 V to 5.5 V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
(2)
Symbol
f
SCL
t
SP
t
LOW
t
HIGH
t
R(1)
t
F(1)
t
HD;STA
t
SU;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
AA
t
DH
t
BUF(1)
t
WC(3)
Parameter
Clock Frequency
Input Filter Spike
Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
(for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a
New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
0.6
0.6
0
100
0.6
900
1.3
0.6
300
300
Min
Max
400
100
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
5
Doc No. 3010, Rev. K
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
