The MD1213DB1 can drive a transducer as a single chan-
nel transmitter for ultrasound and other applications. The
demoboard consists of one MD1213 in a 12-Lead 4x4x0.9mm
QFN (K6) package, combined with Supertex’s TC6320, an
IC containing high voltage P- and N- channel FETs in a 8-
Lead SOIC package.
Logic control inputs INA, INB and OE of the MD1213 are
controlled via the six-pin head connector on the board. Due
to the fast signal rise and fall time requirement, every ground
wire of the ribbon cable must be used to connect from the
logic signal source. When OE is enabled, it should recieve
the same voltage as the logic source circuit’s power supply.
The MD1213DB1 output waveforms can be displayed direct-
ly using an oscilloscope by connecting the scope probe to
the test point TP10-1 and TP10-2 (GND). The J5 jumper can
select whether or not to connect the on-board equivalent-
load, a 220pF 200V capacitor paralleled with a 1.0kΩ, 1W
resistor. Also, a coaxial cable can be used to easily connect
to the user’s transducer.
MD1213DB1
Demoboard Features
►
Demonstrates one channel ultrasound transmitter
►
MD1213 driving a TC6320 power MOSFET
►
±2.0 A source and sink current capability
►
Logic control signal input connector
►
SMA connectors for cable to a transducer
►
1.8 to 3.3V CMOS logic interface
Designing a Pulser with the MD1213
Low input capacitance and fast switching speed are the im-
portant features of the MD1213’s input stage. Its logic inputs
have an input impedance of about 20kΩ in parallel with 5pF,
and an internal speed of around 100MHz. The output enable
pin, OE, determines the threshold voltage for the input-chan-
nel level translators. The MD1213’s input stage logic is fully
compatible with 1.8V, 2.0V, 2.5V, 3.3V, or 5.0V CMOS logic.
The level translators are also compatible with these logic
voltage levels right up to the MOSFET’s gate-driver voltage
level, which is typically 5.0V to 12V. When OE is low, the
chip disables its’ outputs, setting OUTA high and OUTB low.
This condition helps to properly pre-charge the AC coupling
capacitors that the user can optionally add in series with the
gate-driver circuit of the external P/N-channel FET pair.
Block Diagram
V
CC
V
DD
1
OE
INA
OUTA
0 to 100V
1.0µF
XDCF
V
DD
V
DD
2
V
H
VH
VCC
OE
INA
INB
Level
Shifter
V
SS
2
V
DD
2
V
L
V
H
HV
OUT
0 to 100V
INB
OUTB
C
L
R
L
TC6320
1.0µF
MD1213
GND
V
SS
1
V
SS
2
V
SS
Doc.# DSDB-MD1213DB1
A032913
VL
V
L
Supertex inc.
www.supertex.com
MD1213DB1
Designing a Pulser with the MD1213
(cont.)
The MD1213’s output stage has separate power pins that
enable users to select the output signal’s high and low levels
independently from the supply voltages that the main part of
the circuit uses. For example, the input logic levels could be
0V and 3.3V, and the output levels may lie anywhere in the
range of ±5.0V.
Typically, the MD1213’s output has rise and fall times of
about 6.0ns when driving a 1000pF load. The output stage
is capable of peak currents of up to ±2.0A, depending on the
system’s supply voltages and load capacitance. Such high
currents are necessary to drive the input capacitances of the
output MOSFETs for fast switching speeds.
The bottom of the MD1213 12-Lead QFN package has a
thermal pad for power dissipation enhancement. It must ex-
ternally connect to the VSS pin on the PCB. This pad is con-
nected internally to the substrate of the IC circuit. It must
have the lowest potential voltage of the circuit at all times,
including during the power up or down periods, or it could
cause circuit latch-up or damage.
The Supertex TC6320 is comprised of an N- and P-channel
MOSFET pair with low threshold voltages (2.0V maximum).
This 8-Lead SO packaged device features 200V breakdown
voltage, 2.0A peak current output capabilities, and low input
capacitance (110pF maximum). The TC6320 integrates the
gate-source resistors and Zener diodes that a high voltage
pulse-driver requires. The high output current capability of
the TC6320 MOSFET speeds output waveform rise and fall
time, while their low input capacitance minimizes propaga-
tion delays.
During power up/down conditions, the high voltage supplies
V
PP
and V
NN
can inject transient voltages greater than 20V
via the output transistor’s parasitic gate-to-source capaci-
tances. The maximum permissible gate-to-source voltage
(V
GS
) is ±20V. The TC6320’s integral 15 - 18V Zener diodes
across its’ gate and source terminals protect against such
transient voltages. But even if it is possible to slowly ramp
the high voltage supplies, these Zener diodes are still cru-
cial, as they also serve as the DC voltage restoration stage
for the gates.
Note that it is possible to vary the V
PP
and V
NN
voltages with-
out making significant changes to the circuit configuration.
For example, V
NN
can be 0V and V
PP
+200V for positive uni-
polar pulses. Or V
NN
can be -200V and V
PP
0V for a negative
unipolar pulser. If the user plans to operate the demoboard
above 100V, he must adjust the bypass capacitors (C8 or
C16) to a voltage rating of 200V. Due to the BV limitation of
the TC6320, the differential voltage (V
PP
-V
NN
) must not be
greater then 200V.
Operating Supply Voltages
Symbol
V
SS
V
L
V
DD
V
H
V
CC
V
PP
V
NN
Parameter
Negative drive supply
Positive drive supply
Logic supply
TC6320 HV positive supply
TC6320 HV negative supply
Min
-5.5
V
SS
4.5
V
SS
+2.0
1.8
0
-100
Typ
0
-
10
10
3.3
-
-
Max
0
V
DD
-2.0
12
V
DD
5.5
100
0
Units
V
V
V
V
V
Conditions
(V
DD
- V
SS
) ≤ 13
(V
DD
- V
SS
) ≤ 13
---
---
---
Doc.# DSDB-MD1213DB1
A032913
2
Supertex inc.
www.supertex.com
MD1213DB1
Current Consumption
Symbol
I
DD
I
H
I
CC
I
PP
I
NN
Typ
0.7
0.7
58
2.4
2.5
Units
mA
mA
mA
mA
mA
Conditions
V
DD
= 12V
V
H
= 12V
V
CC
= 3.3V
V
PP
= 100V
V
NN
= -100V
Waveform C, 20MHz, 8 cycles, V
SS
= V
L
= 0 Load: 220pF//1.0k
Voltage Supply Power-Up Sequence
1
2
3
4
5
6
V
CC
V
DD
V
SS
V
L
V
H
V
PP
/V
NN
Logic voltage supply, and all OE = INA = INB = Low
Positive drive voltage for V
DD
1,2
0 or -5.0V negative bias voltage for V
SS
1,2 and IC substrate voltage
0 to -5.0V or V
SS
negative driver voltage for V
L
0 to +10 or V
DD
positive driver voltage for V
H
+/-HV supply, slew rate not exceed 2.0V/ms
Note:
The power-down sequence should be the reverse of the power-up sequence above
Board Connector and Test Pin Description
Logic Control Signal Input Connector
Pin
J3-1
J3-2
J3-3
J3-4
J3-5
J3-6
Pin
J1-1
J1-2
J1-3
J1-4
J1-5
J1-6
J2-1
J2-2
J2-3
Name
VCC
OE
GND
INA
GND
INB
Name
VCC
VSS
VL
GND
VDD
VH
VPP
GND
VNN
Description
Logic voltage supply for VCC
MD1213 OE signal for pulser output enable, when OE=0, TC6320 P and N MOSFET both off.
Logic ground
---
Logic ground
---
Description
+3.3 logic voltage supply for V
CC
0 or -5.0V negative bias supply for V
SS
1, V
SS
2 and SUB
0 or -5.0V negative voltage supply for driver output stage
Power supply ground
+10V positive driver voltage supply for V
DD
1 and V
DD
2
+10 or +5.0V positive voltage supply for driver output stage
0 to +100V positive high voltage supply with current limiting maximum to 2.0A
High voltage power supply return, 0V
0 to -100V Negative high voltage supply with current limiting maximum to -2.0A
Power Supply Connector
Doc.# DSDB-MD1213DB1
A032913
3
Supertex inc.
www.supertex.com
MD1213DB1
Schematic Diagram
1
C21
0.1
V
CC
C22
0.1
J3
1
3
5
2
4
6
11
VDD1
OE
INA
FB1
V
DD
2
C24
1.0
TP9
V
H
C20
0.1
VPP
8
VH
OUTA
9
R9
200Ω
C11
1.0µ
100V
3
4
OUTB
7
C10
10n
200V
TP5
1
R14
200Ω
2
2
6
P
5
7
8
1
C12
C8
220
1.0µ
100V
VNN
R15
1.0kΩ
1.0W
2
1
D11
BAV99
3
R10
200Ω
1
3
J5
2
4
R11
200Ω
J6
XDCR
TP10
1
2
U2
MD1213
TP13
12
TP11
1
TP12
3
INB
10
VDD2
1
2
C9
10n
200V
U3
TC6320
N
TP7
GND
4
VSS1 SUB
5
C28
0.1
V
SS
13
VSS2
6
C27
0.1
V
L
VL
2
C25
1.0
TP8
V
SS
TP1
C1
10
16V
+
V
L
TP2
C2
10
16V
V
DD
TP3
V
H
TP4
VDD
6
6
1
VCC
VSS
D2A
D1A
4
D2B
1
4
3
D3B
6
D3A
1
3
VL
D4
B1100-13
1
2
C5
1.0µ
100V
1
C6
1.0µ
100V
2
D5
B1100-13
VH
VPP
VNN
+
C3
10
16V
+
C4
10
16V
TP6
VCC
D1B
3
4
1 2
3
4
J1
5
6
PCB Layout
Doc.# DSDB-MD1213DB1
A032913
+
1
2
J2
3
4
Supertex inc.
www.supertex.com
MD1213DB1
MD1213DB1 Waveforms
Fig 1:
INA, INB, OUTA, OUTB and HV
OUT
with 220pF//1K Load, V
DD
= V
H
=+12V, V
SS
= V
L
= 0V, V
PP
/V
NN
= +/-100V, 10MHz
Fig 2:
INA, INB, OUTA, OUTB and HV
OUT
with 220pF//1K Load, V
DD
= V
H
= +12V, V
SS
= V
L
= 0V, V
PP
/V
NN
= +/-100V, 20MHz
Fig 3 :
INA, INB, OUTA, OUTB and HV
OUT
with 220pF//1K Load, V
DD
= V
H
=+12V, V
SS
= V
L
= 0V, V
PP
/V
NN
= +/-100V, 312.5kHz
Supertex inc.
does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.”
Supertex inc.
does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the
As time goes by, people are increasingly concerned about their own and their families' health. However, existing monitoring devices for individual vital signs have struggled to gain market share du...[详细]
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
