Si5324
A
NY
- F
R E QUE N C Y
P
RECISION
C
LOCK
M
ULTIPLIER
/
J
I T T E R
A
TTENUATOR
Features
Generates any frequency from
2 kHz to 945 MHz and select
frequencies to 1.4 GHz from an
input frequency of 2 kHz to
710 MHz
Ultra-low jitter clock outputs as low
as 290 fs rms (12 kHz–20 MHz),
320 fs rms (50 kHz–80 MHz)
Integrated loop filter with
selectable loop bandwidth
(4– 525 Hz)
Meets ITU-T G.8251 and Telcordia
GR-253-CORE jitter specification
Hitless input clock switching with
phase build-out
Freerun, Digital Hold operation
Configurable signal format per
output (LVPECL, LVDS, CML,
CMOS)
Support for ITU G.709 and custom
FEC ratios (255/238, 255/237,
255/236, 239/237, 66/64, 239/238,
15/14, 253/221, 255/238)
LOL, LOS, FOS alarm outputs
I
2
C or SPI programmable
On-chip voltage regulator with high
PSNR
Single supply 1.8 ±5%, 2.5 ±10%,
or 3.3 V ±10%
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS-compliant
Ordering Information:
See page 64.
Applications
Broadcast video –3G/HD/SD-SDI,
Genlock
Packet Optical Transport Systems
(P-OTS), MSPP
OTN/OTU-1/2/3/4 Asynchronous
Demapping (Gapped Clock)
SONET OC-48/192/768,
SDH/STM-16/64/256 line cards
Pin Assignments
CKOUT1–
CKOUT2+
1/2/4/8/10G Fibre Channel line
cards
GbE/10/40/100G Synchronous
Ethernet (LAN/WAN)
Data converter clocking
Wireless base stations
Test and measurement
CMODE
CKOUT2–
GND
36 35 34 33 32 31 30 29 28
RST
NC
INT_C1B
C2B
VDD
XA
XB
GND
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
RATE1
CKIN2–
CKIN1–
RATE0
VDD
CKIN2+
CKIN1+
LOL
NC
27 SDI
26 A2_SS
25 A1
CKOUT1+
24 A0
23 SDA_SDO
22 SCL
21 CS_CA
20 GND
19 GND
VDD
NC
GND
Pad
Description
The Si5324 is a low-bandwidth, jitter-attenuating, precision clock multiplier
for applications requiring sub 1 ps jitter performance with loop bandwidths
between 4 Hz and 525 Hz. The Si5324 accepts two input clocks ranging
from 2 kHz to 710 MHz and generates two output clocks ranging from 2 kHz
to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided
down separately from a common source. The Si5324 can also use its
external reference as a clock source for frequency synthesis. The device
provides virtually any frequency translation combination across this
operating range. The Si5324 input clock frequency and clock multiplication
ratio are programmable via an I
2
C or SPI interface. The Si5324 is based on
Silicon Laboratories' 3rd-generation DSPLL
®
technology, which provides
any-frequency synthesis and jitter attenuation in a highly integrated PLL
solution that eliminates the need for external VCXO and filter components.
The DSPLL loop bandwidth is digitally programmable, providing jitter
performance optimization at the application level. The Si5324 is ideal for
providing clock multiplication and jitter attenuation in high performance
timing applications.
NC
Rev. 1.1 1/14
Copyright © 2014 by Silicon Laboratories
NC
Si5324
Si5324
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2. Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5. Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
5.1. ICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
8. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
10. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
10.1. Si5324 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Rev. 1.1
3
微控制器 MCU
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