INTEGRATED CIRCUITS
PTN3501
Maintenance and control device
Product specification
Supersedes data of 2000 Nov 22
2001 Jan 17
Philips
Semiconductors
Philips Semiconductors
Product specification
Maintenance and control device
PTN3501
FEATURES
•
I
2
C to parallel port expander
•
Internal 256x8 E
2
PROM
•
Self timed write cycle (5 ms typ.)
•
16 byte page write operation
•
Controlled pull-up on address lines
•
Low voltage V
CC
range of +2.5 V to +3.6 V
•
5 V – tolerant I/Os
•
Low standby current (< 60
µA
)
•
Power on Reset
•
Supports Live Insertion
•
Compatible with SMBus specification version 1.1
•
High E
2
PROM endurance and data retention
•
Available in TSSOP20 package
DESCRIPTION
The PTN3501 is a general purpose maintenance and control device.
It features an on-board E
2
PROM that can be used to store error
codes or board manufacturing data for read–back by application
software for diagnostic purposes.
The eight quasi bidirectional data pins can be independently
assigned as inputs or outputs to monitor board level status or
activate indicator devices such as LEDs.
The PTN3501 has six address pins allowing up to 64 devices to
share the common two wire I
2
C software protocol serial data bus.
The PTN3501 supports live insertion to facilitate usage in removable
cards on backplane systems.
The PTN3501 is an alternative to the functionally similar PTN3500
for systems where a high number of devices are required to share
the same I
2
C-bus without need for an additional I
2
C-bus I/O
expander.
PIN CONFIGURATION
A0
A1
A2
P0
P1
P2
P3
INT
A5
V
SS
1
2
3
4
5
6
7
8
9
10
PTN3501
20
19
18
17
16
15
14
13
12
11
V
DD
SDA
SCL
WC
P7
P6
P5
P4
A3
A4
SW00657
Figure 1.
PIN DESCRIPTION
PIN NUMBER
1,2,3,9,11,12
4,5,6,7
10
13,14,15,16
17
8
18
19
20
SYMBOL
A0:5
P0:3
V
SS
P4:7
WC
INT
SCL
SDA
V
DD
NAME AND FUNCTION
Address Lines
Quasi–bidirectional I/O pins
Ground
Quasi–bidirectional I/O pins
Write Control Pin. Should be
tied LOW.
Interrupt Pin
I
2
C Serial Clock
I
2
C Serial Data
Supply Voltage
ORDERING INFORMATION
Package
Type number
n mber
Name
PTN3501DH
TSSOP20
Description
Plastic thin shrink small-outline package; 20 leads; body width 4.4 mm
Version
SOT360-1
FUNCTIONAL DIAGRAM
INT
SCL
SDA
A5:0
I
2
C
CONTROL
8-BIT
I/O PORT
P7:0
WC
E2PROM
256
×
8
SW00647
Figure 2.
2001 Jan 17
2
853-2227 25436
Philips Semiconductors
Product specification
Maintenance and control device
PTN3501
CHARACTERISTICS OF THE I
2
C-BUS
The I
2
C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 4).
Bit transfer
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 3).
System configuration
A device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 5).
SDA
SCL
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SW00542
Figure 3. Bit transfer
SDA
SDA
SCL
S
START CONDITION
P
STOP CONDITION
SCL
SW00543
Figure 4. Definition of start and stop conditions
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SW00544
Figure 5. System configuration
2001 Jan 17
3
Philips Semiconductors
Product specification
Maintenance and control device
PTN3501
Acknowledge (see Figure 6)
The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set–up and hold times must be
taken into account.
A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
DATA OUTPUT
BY TRANSMITTER
NOT ACKNOWLEDGE
DATA OUTPUT
BY RECEIVER
ACKNOWLEDGE
SCL FROM
MASTER
S
START
CONDITION
1
2
8
9
CLOCK PULSE FOR
ACKNOWLEDGEMENT
SW00545
Figure 6. Acknowledgment on the I
2
C-bus
FUNCTIONAL DESCRIPTION
V
DD
WRITE PULSE
100
µA
DATA FROM
SHIFT REGISTER
D
FF
C
I
S
POWER-ON
RESET
V
SS
P0 TO P7
Q
D
FF
READ PULSE
C
I
S
Q
DATA TO
SHIFT REGISTER
TO INTERRUPT LOGIC
SW00788
Figure 7. Simplified schematic diagram of each I/O
2001 Jan 17
4
Philips Semiconductors
Product specification
Maintenance and control device
PTN3501
Addressing
For addressing, see Figure 8.
SLAVE ADDRESS
SLAVE ADDRESS
S
0
A5
A4
A3
A2
A1
A0
0
A
S
1
A5
A4
A3
A2
A1
A0
0
A
(a) I/O EXPANDER
(b) MEMORY
a.
b.
SW00648
Figure 8. PTN3501 slave addresses
Asynchronous Start
Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The
device does not support a Stop or a repeated Start condition during this time period.
I/O OPERATIONS (see also Figure 7)
Each of the PTN3501’s eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port to the
microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9).
SCL
1
2
3
4
5
6
7
8
SLAVE ADDRESS (I/O EXPANDER)
DATA TO PORT
DATA TO PORT
SDA
S
0
A5
A4
A3 A2
A1
A0
0
A
DATA 1
A
DATA 2
A
START CONDITION
WRITE TO
PORT
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
DATA OUT
FROM PORT
t pv
DATA 1 VALID
t pv
DATA 2 VALID
SW00649
Figure 9. I/O WRITE mode (output)
SLAVE ADDRESS (I/O EXPANDER)
DATA FROM PORT
DATA FROM PORT
SDA
S
0
A5
A4
A3 A2
A1
A0
1
A
DATA 1
A
DATA 4
1
P
START CONDITION
READ FROM
PORT
R/W
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM MASTER
STOP
CONDITION
DATA INTO
PORT
DATA 1
t ph
DATA 2
DATA 3
t ps
DATA 4
INT
t iv
t ir
SW00650
Figure 10. I/O READ mode (input)
2001 Jan 17
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