CH, CHA
www.vishay.com
Vishay Sfernice
AEC-Q200 Qualified
High Frequency 70 GHz Thin Film Chip Resistor
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Operating frequency 70 GHz
AEC-Q200 qualified (CHA02016 flip chip only)
Thin film microwave resistors
Flip chip, wraparound or one face termination
Small size, down to 20 mils by 16 mils
Edged trimmed block resistors
Pure alumina substrate (99.5 %)
Ohmic range: 10R to 500R
Design kits available
Modelithics
®
library available
Small internal reactance (LC down to 1 x 10
-24
)
Tolerance 1 %, 2 %, 5 %
TCR: 100 ppm/°C in (-55 °C, +155 °C) temperature range
TCR: 50 ppm/°C available upon request for 10
Ω
to150
Ω
ohmic range
• Material categorization: for definitions of compliance
please see
www.vishay.com/doc?99912
LINKS TO ADDITIONAL RESOURCES
D
D
3
3
3D Models
S-Parameters
Simulation
Tools
Application
Notes
Capabilities and
Custom Options
Did You
Know?
Infographics
Why It
Matters
Those miniaturized components are designed in such a way
that their internal reactance is very small. When correctly
mounted and utilized, they function as almost pure resistors
on a very large range of frequency, up to 50 GHz, and
70 GHz for CH02016 from 50
Ω
to 100
Ω.
STANDARD ELECTRICAL SPECIFICATIONS
MODEL
CH02016
CH0402
CH0603
SIZE
02016
0402
0603
RESISTANCE
RANGE
Ω
10 to 500
10 to 500
10 to 500
RATED POWER
Pn
W
0.030
0.050
0.125
LIMITING ELEMENT
TOLERANCE
VOLTAGE
±%
V
30
1, 2, 5
37
1, 2, 5
50
1, 2, 5
TEMPERATURE
COEFFICIENT
± ppm/°C
100 (50 upon request)
100 (50 upon request)
100 (50 upon request)
DIMENSIONS
in millimeters (inches)
CH02016 F / CH02016 P / CH0402 P / CH0603 P
D
A
D
C
G
F
B
B
CH0402 F / CH0603 F
A
D
D
C
CH0402 N / CH0402 G /CH0603 N / CH0603 G
D
A
D
C
E
E
B
CASE SIZE
MODEL /
TERMINATION
CH02016 F
CH02016 P
CH0402 F
CH0402 N
CH0402 G
CH0402 P
CH0603 F
CH0603 N
CH0603 G
CH0603 P
Note
(1)
± 0.070 (± 0.003)
Revision: 22-Nov-2021
A
± 0.10 (± 0.004)
0.480 (0.020)
1.000 (0.040)
1.200 (0.047)
1.520 (0.060)
1.720 (0.068)
B
± 0.10 (± 0.004)
0.390 (0.016)
0.600 (0.023)
0.600 (0.023)
0.750 (0.030)
0.750 (0.030)
DIMENSIONS
C
± 0.127 (± 0.005)
0.420 (0.016)
(1)
0.500 (0.020)
0.500 (0.020)
0.500 (0.020)
0.500 (0.020)
D
E when applicable
MIN.
MAX.
0.110
0.150
(0.004)
(0.006)
0.150
(0.006)
0.110
(0.004)
0.250
(0.010)
0.235
(0.009)
0.350
(0.014)
0.150
(0.006)
0.510
(0.020)
0.275
(0.011)
F
± 0.050 (± 0.002)
0.260 (0.010)
n/a
0.320 (0.013)
n/a
0.660 (0.026)
G
± 0.050 (± 0.002)
0.300 (0.012)
n/a
0.880 (0.035)
n/a
1.355 (0.053)
Document Number: 53014
1
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH, CHA
www.vishay.com
Vishay Sfernice
TOLERANCE VS. OHMIC VALUES
Ohmic range
Tolerance CH02016
Tolerance CH0402 and CH0603
10
Ω ≤
R
< 50
Ω
5%
2 %, 5 %
50
Ω ≤
R
≤
500
Ω
1 % for 50
Ω
and 100
Ω,
2 %, 5 %
1 %, 2 %, 5 %
LAND PATTERN FOR F “FLIP CHIP” TERMINATIONS
in millimeters (inches)
G
min.
X
max.
Z
max.
CHIP SIZE
02016
0402
0603
Z
max.
0.53 (0.021)
1.40 (0.055)
1.71 (0.067)
X
max.
0.44 (0.017)
0.65 (0.026)
0.90 (0.035)
G
min.
0.15 (0.006)
0.40 (0.016)
0.76 (0.030)
Note
• Suggested land pattern: according to IPC-7351
LAND PATTERN FOR N AND G WRAPAROUND TERMINATIONS
in millimeters (inches)
G
min.
Z
max.
CHIP SIZE
0402
0603
Z
max.
1.55 (0.061)
2.37 (0.093)
G
min.
0.15 (0.006)
0.35 (0.014)
X
m
ax
.
X
max.
0.73 (0.029)
0.98 (0.039)
Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A
“Generic Requirements for Surface Mount Design and Land Pattern Standard”
PERFORMANCE (CH02016 F TERMINATION)
TEST PROCEDURES AND REQUIREMENTS
AEC-Q200
CLAUSE
TEST
PROCEDURE
MIL-STD-202 method 108
1000 h at T = 125 °C,
unpowered
JESD22 method JA-104
1000 cycles (-55 °C to +155 °C)
MIL-STD-202 method 103
1000 h 85 °C / 85 % RH
10 % of operating power
GLOBAL
PERFORMANCES
± 2 % ± 0.05
Ω
± 1.8 % ± 0.05
Ω
± 2 % ± 0.05
Ω
TYPICAL
PERFORMANCES
(25
Ω
TO 250
Ω)
± 0.2 % ± 0.05
Ω
± 1.5 % ± 0.05
Ω
± 0.75 % ± 0.05
Ω
3
High temperature exposure
4
Temperature cycling
7
Biased humidity
Revision: 22-Nov-2021
Document Number: 53014
2
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH, CHA
www.vishay.com
TEST PROCEDURES AND REQUIREMENTS
AEC-Q200
CLAUSE
TEST
PROCEDURE
MIL-STD-202 method 108
Condition D steady state
T = 125 °C at rated power
90' on / 30' off / 1000 h
MIL-STD-202 method 213
condition C
100
g/6
ms 3.75 m/s
3 shock/direction,
2 directions along 3 axes (18 shocks)
MIL-STD-202 method 204
5 g for 20 min,
12 cycles each of 3 orientations
Test from 10 Hz to 2000 Hz
MIL-STD-202 method 210
condition D
Flux used: alpha 611
Solder temp.: 260 °C ± 5 °C
Total immersion during 10 s
AEC-Q200-002
J-STD-002
- Preconditioning 4 h dry heat
aging and 235 °C SnPb 5 s
- 215 °C SnPb 5 s
- 260 °C SnAgCu 10 s
UL 94
AEC-Q200-005
AEC-Q200-001
GLOBAL
PERFORMANCES
TYPICAL
PERFORMANCES
(25
Ω
TO 250
Ω)
± 1 % ± 0.05
Ω
Vishay Sfernice
8
Operational life
± 2.5 % ± 0.05
Ω
13
Mechanical shock
± 0.05 % ± 0.05
Ω
± 0.015 % ± 0.05
Ω
14
Vibration
± 0.1 % ± 0.05
Ω
± 0.05 % ± 0.05
Ω
15
Resistance to soldering heat
± 2.5 % ± 0.05
Ω
± 0.5 % ± 0.05
Ω
17
ESD
Classification 1C
1000 V
DC
to 2000 V
DC
18
Solderability
Good tinning (≥ 95 % covered)
No visible damage
20
21
24
Flammability
Board flex
Flame retardance
Class V-0
No burning
± 0.1 % ± 0.05
Ω
± 0.05 % ± 0.05
Ω
No flame, no explosion,
no temperature higher than 350 °C
PREFERRED MODELS AND VALUES
Vishay Sfernice highly recommend to use the smallest sizes and flip chip version to get the best performances.
Recommended Values:
10R/18R/25R/50R/75R/100R/150R/180R/200R/250R/330R
/500R
Those values are available with a
MOQ of 100 pieces.
Recommended termination:
F
Recommended tolerance:
2%
Other values can be ordered upon request, but higher
MOQ will apply: 1000 pieces for CH02016, 500 pieces for
CH0402, 250 pieces for CH0603.
DESIGN KITS
Design kits are available Ex Stock in CH02016 and CH0402 sizes. There are 20 pieces per recommended value. F termination.
5 % tolerance.
Those kits are packaged in pieces of tape and delivered in ESD bags.
Revision: 22-Nov-2021
Document Number: 53014
3
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH, CHA
www.vishay.com
PACKAGING
Standard packaging is plastic tape and reel for all sizes.
Paper tape and reel is available for sizes 0402 and 0603.
Waffle pack is available for all sizes.
Depending on the type of terminations, parts will be packed differently:
One face:
• Gold terminations:
(P termination option):
Active face up.
Please use M termination code for active face down in tape and reel.
• Tin / silver terminations: (F termination option):
Active face down in tape and reel.
Active face up in waffle pack.
Note
• Please refer to Vishay Sfernice Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Products” for soldering
recommendation (document number 52029, 3. Guidelines for Surface Mounting Components (SMD), profile number 3 applies
NUMBER OF PIECES PER PACKAGE
TAPE AND REEL
WAFFLE PACK
2" x 2"
MIN.
MAX.
484
100
100
5000
100
Vishay Sfernice
SIZE
02016
0402
0603
MOQ
See MOQ mentioned
on preferred models
and values
TAPE WIDTH
8 mm
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover. To get
“not stacked up” waffle pack in case of ordered quantity
> maximum number of pieces per package: please consult
Vishay Sfernice for specific ordering code.
Tape and Reel
See Part Numbering information to get the quantity desired
by tape.
In regard to the CH02016 size only, up to 5 empty cavities
can be found every 1000 parts in the reel. Nevertheless, the
number of requested parts will be respected.
GLOBAL PART NUMBER INFORMATION
New Global Part Numbering: CH0402-50RJF (preferred part number format)
AEC-Q200 Version Part Numbering: CHA02016-xxxxx
C
H
0
4
SIZE
02016
0402
0603
0
2
-
5
TOLERANCE
F
=1%
G
=2%
J
=5%
0
R
J
F
T
PACKAGING
9
9
9
GLOBAL MODEL
CH, CHA
OHMIC VALUE
10R to 500R
TERMINATION
F
(flip chip):
SnAg over nickel barrier
N
(W/A):
SnAg over nickel barrier
(except 02016)
P
(one face):
(1)
gold bonding pads
G
(W/A): gold over nickel
barrier
(except 02016)
OPTION
From
1 to 3 digits.
Leave blank
if no option.
For more
information see
Codification of
Packaging table
AEC-Q200 Part Number Example: CHA02016-100RJFTF
(AEC-Q200 qualified CH series, 100
Ω,
5 % tolerance, 5000 pieces reels)
Historical Part Number Example: CH02016-100RGFPT1K (tapes of 1000 pieces)
CH0402-50RJF
(waffle pack)
CHKIT Part Numbers
(2)
:
CHKIT-02016
CHKIT-0402
Notes
• Historical part numbers are not recommended but can still be used for ordering
(1)
Gold termination for application in hermetic package. Can also be mounted on PCB with SnAg solder paste.
Please use M termination code for active face down in tape and reel
(2)
CHKIT for 0603 size is not available
Revision: 22-Nov-2021
Document Number: 53014
4
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
CH, CHA
www.vishay.com
Vishay Sfernice
CODIFICATION OF PACKAGING
WAFFLE PACK (available for all sizes)
W
PLASTIC TAPE (standard packaging for all sizes)
T
TA
TB
TC
TD
TF
PAPER TAPE (available for 0402 and 0603)
PT
PA
PB
PC
100 min., 1 mult.
100 min., 100 mult.
250 min., 250 mult.
500 min., 500 mult.
100 min., 1 mult.
100 min., 100 mult.
250 min., 250 mult.
500 min., 500 mult.
1000 min., 1000 mult.
Full tape (quantity depending on size of chips)
100 min., 1 mult.
TYPICAL HIGH FREQUENCY PERFORMANCE ELECTRICAL MODEL
Z
C
Z
0
C
g
L
c
L
R
L
c
C
g
Z
0
C
L
R
Z
L
c
C
g
Internal shunt capacitance
Internal inductance
Resistance
Internal impedance (R, L, C)
External connection inductance
External capacitance to ground
The complex impedance of the chip resistor is given by the following equations:
R
+
jω
(
L
–
R
C
–
L Cω
)
-
Z
=
-------------------------------------------------------------------------------------
2
2
2
4
1
+
C
[ (
R
C
–
2L
)ω
+
L Cω
]
[
Z
]
1
-
-------
=
-----------------------------------------------------------------------------------------
x
-
2
2
2
4
R
1
+
C
[ (
R
C
–
2L
)ω
+
L Cω
]
2
2
2
2
ω (
L
–
R
C
–
L Cω
)
-
1
+
-----------------------------------------------------------
R
2
2
2
2
2
2
Notes
•
ω
=2x
π
x
f
•
f:
frequency
–
1
ω (
L
–
R
C
–
L Cω
)
-
θ
=
tan
-----------------------------------------------------------
R
R, L and C are relevant to the chip resistor itself.
L
c
and C
g
also depend on the way the chip resistor is mounted.
It is important to notice that after assembly the external reactance of L
c
and C
g
will be combined to internal reactance of L and
C. This combination can upgrade or downgrade the HF behavior of the component.
This is why we are displaying three sets of data:
[
Z
]
-
•
-------
versus frequency curves which aim to show at a glance the intrinsic HF performance of a given chip resistor
R
[
Z
total
]
-
•
------------------
versus frequency curves which aim to show the behavior of the chip resistor when mounted
R
Revision: 22-Nov-2021
Document Number: 53014
5
For technical questions, contact:
sferthinfilm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
