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5962-9560003MYA

产品描述Standard SRAM, 512KX8, 25ns, CMOS, TSOP-32
产品类别存储    存储   
文件大小1MB,共41页
制造商Microsemi
官网地址https://www.microsemi.com
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5962-9560003MYA概述

Standard SRAM, 512KX8, 25ns, CMOS, TSOP-32

5962-9560003MYA规格参数

参数名称属性值
Objectid2078447937
包装说明TSOP-32
Reach Compliance Codeunknown
ECCN代码3A991.B.2.A
最长访问时间25 ns
I/O 类型COMMON
JESD-30 代码R-XDSO-G32
JESD-609代码e0
长度41.91 mm
内存密度4194304 bit
内存集成电路类型STANDARD SRAM
内存宽度8
功能数量1
端子数量32
字数524288 words
字数代码512000
工作模式ASYNCHRONOUS
最高工作温度125 °C
最低工作温度-55 °C
组织512KX8
输出特性3-STATE
封装主体材料UNSPECIFIED
封装代码SOP
封装等效代码SOP32,.56
封装形状RECTANGULAR
封装形式SMALL OUTLINE
并行/串行PARALLEL
电源5 V
认证状态Not Qualified
筛选级别MIL-STD-883
座面最大高度3 mm
最大待机电流0.025 A
最小待机电流4.5 V
最大压摆率0.225 mA
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子面层TIN LEAD
端子形式GULL WING
端子节距1.27 mm
端子位置DUAL
宽度10.7442 mm

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REVISIONS
LTR
C
DESCRIPTION
Change minimum dimensions A, b, and E for case outline U. Add
CAGE 65786 as a source of supply. Editorial changes throughout. -
ksr
Change case outline 9, dimension A from .114 inches to .130 inches. -
glg
Added low-power devices 09 - 14 to drawing. Removed CAGE
0EU86 for devices 05 - 08. - glg
Changed minimum dimension b for package "U" from 0.015 inches to
0.012 inches. - glg
Changed minimum dimension b for package "M" from 0.019 inches to
0.012 inches. Updated boilerplate paragraphs. ksr
Table I; Changed the I
OL
from 8 mA to 6 mA V
OL
test. Added device
types 15 and 16. Editorial changes throughout. -sld
Add case outline 7. Add CAGE 0EU86 as source of supply for case
outline 7. Editorial changes throughout. tcr
Add device 17 and add case outline 6. Add CAGE 6S055 as source
of supply for case outline 6. Some editorial changes. ksr
Update drawing to meet current MIL-PRF-38535 requirements. - glg
DATE
97-10-24
APPROVED
Raymond Monnin
D
E
F
G
H
J
K
L
00-03-01
00-11-22
00-12-13
02-02-12
04-05-25
08-08-18
09-01-22
16-09-01
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Raymond Monnin
Robert M. Heber
Robert M. Heber
Charles Saffle
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
L
15
L
16
L
17
L
18
REV
SHEET
PREPARED BY
Jeff Bowling
L
19
L
20
L
21
L
1
L
22
L
2
L
23
L
3
L
24
L
4
L
25
L
5
L
26
L
6
L
27
L
7
L
28
L
8
L
29
L
9
L
30
L
10
L
31
L
11
L
32
L
12
L
13
L
14
DLA LAND AND MARITIME
COLUMBUS, OHIO 43218-3990
http://www.landandmaritime.dla.mil/
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS
AVAILABLE
FOR USE BY All
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
CHECKED BY
Jeff Bowling
APPROVED BY
Michael. A. Frye
DRAWING APPROVAL DATE
96-03-05
REVISION LEVEL
L
MICROCIRCUITS, MEMORY, DIGITAL,
CMOS, 512K X 8 STATIC RANDOM
ACCESS MEMORY (SRAM),
MONOLITHIC SILICON
SIZE
A
SHEET
1 OF
32
5962-E505-16
CAGE CODE
67268
5962-95600
DSCC FORM 2233
APR 97

 
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