TC7WG74FU/FK
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC7WG74FU,TC7WG74FK
D-Type Flip Flop with Preset and Clear
Features
•
•
•
•
•
High-speed
: f
MAX
= 246 MHz (Typ.)
at V
CC
= 3 V, CL=15pF
High-level output current : ±8 mA (min) at V
CC
= 3 V
Operation voltage range
5.5-V tolerant inputs
3.6-V power down protection outputs
(SM8)
TC7WG74FK
TC7WG74FU
: V
CC
(opr)=0.9 to 3.6V
Marking
SM8
Product name
US8
(US8)
WG
74
Weight
SSOP8-P-0.65 : 0.02 g (typ.)
SSOP8-P-0.50A : 0.01 g (typ.)
G 74
Lot No.
Absolute Maximum Ratings
Characteristics
Power supply voltage
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−0.5
to 4.6
−0.5
to 7.0
−0.5
to 4.6
−0.5
to V
CC
+
0.5
−20
−20
±25
±100
300 (SM8)
200 (US8)
−65
to 150
(Note 3)
(Note 1)
(Note 2)
Unit
V
V
V
mA
mA
mA
mA
mW
°C
Pin Assignment
(top view)
CK 1
D 2
8 V
CC
D
CK
7
PR
PR CLR
Q
3
Q
GND 4
6
CLR
Q
5Q
Note:
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even
if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum
ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test report
and estimated failure rate, etc).
V
CC
= 0V
High or Low State. I
OUT
absolute maximum rating must be observed.
V
OUT
< GND
Note 1:
Note 2:
Note 3:
1
2009-09-18
TC7WG74FU/FK
AC Electrical Characteristics
(unless otherwise specified, Input : t
r
= t
f
= 3 ns )
Test condition
Characteristic
Symbol
V
CC
(V)
0.9
1.1 to 1.3
1.4 to 1.6
CL = 10 pF
1.65 to
1.95
2.3 to 2.7
3.0 to 3.6
0.9
1.1 to 1.3
Propagation deley time
( CK – Q , Q )
t
pLH
t
pHL
1.4 to 1.6
CL = 15 pF
1.65 to
1.95
2.3 to 2.7
3.0 to 3.6
0.9
1.1 to 1.3
1.4 to 1.6
CL = 30 pF
1.65 to
1.95
2.3 to 2.7
3.0 to 3.6
0.9
1.1 to 1.3
1.4 to 1.6
CL = 10 pF
1.65 to
1.95
2.3 to 2.7
3.0 to 3.6
0.9
1.1 to 1.3
Propagation deley time
( CLR , PR – Q , Q )
t
pLH
t
pHL
1.4 to 1.6
CL = 15 pF
1.65 to
1.95
2.3 to 2.7
3.0 to 3.6
0.9
1.1 to 1.3
1.4 to 1.6
CL = 30 pF
1.65 to
1.95
2.3 to 2.7
3.0 to 3.6
Min.
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Ta = 25°C
Typ.
36.6
15.7
8.0
5.9
3.8
3.0
40.8
17.1
8.8
6.4
4.1
3.3
54.8
22.6
11.4
8.2
5.2
4.1
46.9
18.8
9.5
6.9
4.3
3.3
50.1
20.2
10.1
7.3
4.5
3.6
64.4
25.6
12.6
9.0
5.6
4.4
Max.
Ta =
−
40 to 85°C
Min.
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Max.
Unit
⎯
23.2
10.5
7.4
4.7
3.8
⎯
34.6
11.5
7.9
5.1
4.2
⎯
25.3
11.5
8.1
5.1
4.1
⎯
38.5
12.7
ns
8.6
5.5
4.5
⎯
34.7
15.0
10.3
6.3
5.0
⎯
54.4
16.8
10.8
6.6
5.3
⎯
27.8
12.4
8.7
5.3
4.2
⎯
45.2
14.0
9.1
5.7
4.6
⎯
29.8
13.2
9.2
5.6
4.5
⎯
49.4
15.1
ns
9.7
6.2
4.9
⎯
39.2
16.8
11.3
6.8
5.3
⎯
64.6
19.1
11.8
7.1
5.6
5
2009-09-18
FPGA/CPLD
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