www.fairchildsemi.com
TMC2302A
Image Manipulation Sequencer
40 MHz
Features
• Asynchronous loading of control parameters
• Rapid (25ns per pixel) rotation, warping, panning, and
scaling of images
• Three-dimensional image addressing capability
• General third-order polynomial transformations in two
dimensions on-chip
• Three-dimensional transformation of up to order 1.5 also
supported
• Flexible, user-configurable pixel datapath timing structure
• Static convolutional filtering of up to 16 x 16 Pixel (one-
pass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel
(three-pass) windows
• User-selectable source image subpixel resolution of
2
-8
to 2
-16
• Pin-compatible upgrade to TMC2302
• 24-bit (optional 36-bit) positioning precision within the
source image space, 48-bit internal precision
• Low power CMOS process
• Available in a 120-pin Plastic Pin Grid Array and 120-lead
Metric Quad Flat Pack
Applications
•
•
•
•
•
High-performance video special-effects generators
Guidance systems
Image recognition
Robotics
High-precision image registration
Preliminary Information
Description
The TMC2302A, a pin-compatible replacement for the
TMC2302, is a high-speed self-sequencing address genera-
tor which supports image manipulations such as rotation,
rescaling, warping, filtering, and resampling. It remaps the
pixel locations of a target (display) space back into those of a
source image space. The degree and type of image manipula-
tion is determined by the remapping selected.
To remap from the target to the source space, this integrated
circuit computes a series of polynomials of the target space
coordinates, based on user-assigned coefficients. Two
TMC2302A chips can generate third-order warps of a two-
dimensional image, whereas three can second-order warp a
three-dimensional image.
Simplified Block Diagram
OES
IDAT
15-0
ASYNCHRONOUS
HOST INTERFACE
IADR
6-0
ICS
IWR
WALK
COUNTER
SYNC
NOOP
SYNCHRONOUS
HOST INTERFACE
INIT
CONTROL
PARAMETER
REGISTERS
SOURCE
ADDRESS
GENERATOR
SADR
23-0
SVAL
OEK
KADR
7-0
ACC
TWR
OET
CONTROL
TARGET
ADDRESS
GENERATOR
TADR
11-0
TVAL
END
SYNC FLAGS
DONE
65-2302-01
SOURCE MEMORY
INTERFACE
CONVOLUTIONAL
CONTROL
TARGET
MEMORY
INTERFACE
CLK
Rev. 0.9.2
TMC2302A
PRODUCT SPECIFICATION
Description
(continued)
A system based on two TMC2302As can nearest-neighbor
resample a two-dimensional 512 x 512 pixel image in 6.5
milliseconds, translating, rotating, or warping it, depending
on the user-selected transformation parameters. A complete
bilinear interpolation of the sample image can be completed
in 26 milliseconds (or 6.5ms with a TMC2246A companion
chip), while a nearest-neighbor resampling of a 3D image
128 pixels on a side takes only 53 milliseconds with three
TMC2302As. Image resampling speed is independent of
angle of rotation, degree of warp, or amount of zoom speci-
fied.
The TMC2302A can process image data fields with up to 24
bits of binary resolution (2
24
pixels) per dimension, with 0 to
16-bit subpixel resolution.
Along with the original Plastic Pin Grid Array (PPGA)
package, the TMC2302A is offered in a 120-lead Metric
Quad FlatPack (MQFP) as well. All TMC2302 electrical,
functional, and environmental specifications are improved or
remain unchanged in the TMC2302A.
Preliminary Information
Block Diagram
SOURCE MEMORY
INTERFACE
ASYNCHRONOUS
HOST INTERFACE
SOURCE
(47-24)
ADDRESS
GENERATOR
CONTROL
PARAMETER
AND ADDRESS
BUFFER
48-BITS
KERNEL WALK
OFFSET
ACCUMULATOR
24-BITS
36-BITS
CONVOLUTIONAL
CONTROL
(23-12)
(7-0)
WALK
COUNTER
8-BITS
SYNCHRONOUS
HOST INTERFACE
TARGET MEMORY
INTERFACE
TWR
NOOP
INT
CONTROL
INTERNAL
CLOCK
X(11-0)
Y(11-0)
Z(11-0)
3-D BOUNDARY
COMPARATOR
TARGET
ADDRESS
GENERATOR
3 X 13-BITS
3 x 13 BITS
END
TADR11-0
OET
KADR7-0
OEK
ACC
SADR23-0
OES
BOUNDARY
COMPARATOR
SVAL
IDAT15-0
IADR6-0
ICS
IWR
CLK
SYNC
TVAL
PROGRAMMABLE
DELAY
0 TO 7 CLOCKS
DONE
65-2302-02
2
PRODUCT SPECIFICATION
TMC2302A
Functional Description
General Information
The TMC2302A is a versatile, high-performance address
generator which can control, under user direction, filtering or
remapping of two or three-dimensional images by resam-
pling them from one set of Cartesian coordinates (x, y, z)
into a new, transformed set (u, v, w). Most applications
utilize two identical devices for two-dimensional, or three
devices for three-dimensional, image processing. The host
CPU initializes the system by loading the input image buffer
RAM with the source image pixel data and the TMC2302As
with the image transformation and system configuration con-
trol parameters. These parameters are loaded by a separate,
asynchronous input clock. The IMS-based system then exe-
cutes the entire transformation as programmed, generating a
DONE flag upon completion of the transform. The user can
program the chip to repeat the transform continuously or to
halt at the end.
The IMSs continuously compute the target bit plane (u, v) or
bit space addresses (u, v, w) in typical line-by-line, raster-
scan serial sequence. For each output pixel address, they
compute the corresponding remapped source image coordi-
nates, each of whose upper 24 bits become the source bit
plane addresses (x, y). An additional lower twelve bits are
available through the target address port in the optional
extended address mode. Source image addresses may be
generated at up to 40MHz, with the corresponding target
image addresses then appearing at up to (40/k)MHz, where
“k” is the size of the interpolation kernel implemented. In the
two-IMS system, one TMC2302A computes the horizontal
coordinates x and u while the other generates the y and v
(vertical) addresses. In a three-dimensional system, one
additional IMS would provide the z and w (depth or time)
coordinates.
To support a wide range of image transformations, the “row”
or x/u device implements a 16-term polynomial of the form:
x = a + bu + cu
2
+ du
3
+ ev + fvu + gvu
2
+ hvu
3
+ iv
2
+ jv
2
u + kv
2
u
2
+ lv
2
u
3
+ mv
3
+ nv
3
u + ov
3
u
2
+ pv
3
u
3
where "a" through "p" are the user-defined image transfor-
mation parameters. The TMC2302A steps sequentially
through the pixels within a user-defined rectangle in the tar-
get image space, computing the “old” source image address
(x, y, z) corresponding to each “new” target image pixel (u,
v, w). User-programmable flags are available to indicate
when the source and target image addresses have fallen out-
side of a defined rectangular area, simplifying the generation
of complex images or image windows. Here, u = U-UMIN
and v = V-VMIN, where (u,v) is the target address output by
the TMC2302A.
In the three-dimensional mode, the x/u transformation equa-
tion is:
x = a + bu + ev + kw + fuv + ivw + luw + juvw
See “The Image Transformation Polynomial” section of the
Applications Discussion.
Preliminary Information
(XMIN, YMIN) x
y
ORIGINAL (SOURCE) IMAGE
(UMIN, VMIN) U
V
NEW (TARGET) IMAGE
NEW PIXEL
(U0, V0)
NOTE 2
NOTE 1
(XMAX, YMAX)
Notes:
1. Coordinate transformation U, V pixel mapped into X, Y coordinates.
2. Bilinear pixel interpolation walk. New U, V pixel intensity calculated from surrounding X, Y pixel neigborhood.
(UMAX, VMAX)
65-2302-03
Figure 1. Image resampling geometry showing two-dimensional image rotation and expansion
3
TMC2302A
PRODUCT SPECIFICATION
Preliminary Information
The TMC2302A utilizes an external multiplier-accumulator
or interpolator, connected to the system clock, to calculate
the interpolated pixel value for each color. The products of
the original source image pixel values surrounding the
remapped pixel location (interpolation kernel) and the appro-
priate weights stored in the coefficient lookup table are
summed. The resulting new interpolated image pixel value is
then stored in the corresponding (u, v, w) memory location in
the target image memory buffer. Next, the target image
address is incremented by one in the “u” direction until
UMAX is reached (end of line), when u is reset to UMIN,
and the v counter is incremented to give the first pixel loca-
tion in the next line. The process is repeated, proceeding
line-by-line through the image, until VMAX is reached. In
the case of three-dimensional images, the IMS system also
steps through each page in the image, incrementing in the
“w” direction with the completion of each image plane until
WMAX is reached, and the transformation is complete.
The Image Manipulation Sequencer can support any nearest-
neighbor, bilinear interpolation, or cubic convolution resam-
pling. Interpolation kernels of more than one pixel require an
external interpolation coefficient lookup table and multiplier-
accumulator or multiple multiplier array. One, two, and
three-pass algorithms are supported. For each output point in
a typical two-dimensional single-pass static image filter, the
TMC2302A implements a spiralling pixel resampling algo-
rithm, “walking” around the resampling neighborhood in
two dimensions and generating the appropriate coefficient
table addresses to sum up the interpolated pixel value in the
external pixel interpolator. At the end of each walk, the
TMC2302A will advance one pixel along the output scan
line and then execute the walk for that next pixel. When per-
forming multiple-pass interpolation, the TMC2302A system
proceeds along only one dimension per pass, which requires
dimensionally separable, preferably orthogonal, coefficients.
A basic, two-dimensional TMC2302A-based system is
shown in Figure 2
.
In this typical arrangement, two Image
Manipulation Sequencers process the image. The only other
components needed beyond the source and target image
buffer memories are a multiplier-accumulator or pixel inter-
polator such as the TMC2246A Image Mixer or TMC2250A
Matrix Multiplier, and the Interpolation Coefficient Lookup
Table RAM or ROM.
IMAGE DATA IN
8
16
INITIALIZATION
DATA
IDAT15-0
SADR23-8
ACC
TWR
16
2 x 16
SOURCE
ADDRESS
CONTROL
TMC2302A
ROW (X)
IDAR6-0
SOURCE
IMAGE
BUFFER
RAM
TADR11-0
KADR7-0, SADR7-0
16
X
ADDRESS
INTERPOLATION
COEFFICIENT
DATA BUFFER RAM DATA
IN
OUT
CLOCK
Y
ACC
X, Y, P
MULTIPLIER-
ACCUMULATOR
8
ADDRESS
8
SADR7-0
SADR23-8
IDAT15-0
TMC2302A
ROW (Y)
IDAR6-0
2 x 24
TADR11-0
16
WR
DESTINATION
ADDRESS
DESTINATION
IMAGE
BUFFER
RAM
8
CLOCK
IMAGE DATA OUT
65-2302-04
8
Figure 2. Basic two-dimensional image convolver using TMC2302A IMS with typical 8-bit data path
4
PRODUCT SPECIFICATION
TMC2302A
Pin Assignments
120 Pin Plastic Pin Grid Array, PPGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
65-2302-05
2
3
4
5
6
7
8
9
10 11 12 13
KEY
Top View
Cavity Up
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
Name
GND
SADR
16
SADR
17
V
DD
SADR
21
OES
IADR
6
IADR
3
IADR
0
IDAT
15
IDAT
12
IDAT
9
V
DD
SADR
14
SADR
15
V
DD
SADR
18
SADR
20
SADR
23
IADR
4
IADR
2
ICS
IDAT
13
IDAT
11
IDAT
8
IDAT
7
SADR
13
V
DD
V
DD
GND
Pin
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
Name
SADR
19
SADR
22
IADR
5
IADR
1
IDAT
14
IDAT
10
GND
GND
IDAT
6
SADR
11
SADR
12
GND
V
DD
IDAT
5
IDAT
4
SADR
9
SADR
10
GND
GND
IDAT
3
IDAT
2
SADR
7
SADR
8
V
DD
V
DD
GND
IDAT
1
SADR
6
GND
V
DD
Pin
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
Name
GND
V
DD
IDAT
0
SADR
5
SADR
4
GND
GND
V
DD
SYNC
SADR
3
SADR
2
V
DD
V
DD
CLK
IWR
SADR
1
SADR
0
GND
V
DD
INIT
GND
SVAL
V
DD
NC
V
DD
GND
KADR
0
V
DD
TADR
4
TADR
8
Pin
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Name
DONE
V
DD
GND
NOOP
ACC
OEK
KADR
6
KADR
4
KADR
2
OET
TADR
0
TADR
3
TADR
6
TADR
9
GND
GND
TVAL
GND
KADR
7
KADR
5
KADR
3
KADR
1
TWR
TADR
1
TADR
2
TADR
5
TADR
7
TADR
10
TADR
11
ENDD
Preliminary Information
5
PCB设计
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
