CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
2. Short Circuit may be applied to ground or to either supply.
Electrical Specifications
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Large-Signal Voltage Gain
T
A
= 25
o
C, V+ = 15V, V- = 0V, Unless Otherwise Specified
CA3160
SYMBOL
|V
IO
|
|I
IO
|
I
I
A
OL
TEST CONDITIONS
V
S
=
±7.5V
V
S
=
±7.5V
V
S
=
±7.5V
V
O
= 10V
P-P
, R
L
= 2kΩ
MIN
-
-
-
50
94
TYP
6
0.5
5
320
110
90
-0.5 to 12
32
13.3
0.002
15
0
22
20
10
2
8
MAX
15
30
50
-
-
-
10
320
-
0.01
-
0.01
45
45
15
3
-
MIN
-
-
-
50
94
80
0
-
12
-
14.99
-
12
12
-
-
-
CA3160A
TYP
2
0.5
5
320
110
95
-0.5 to 12
32
13.3
0.002
15
0
22
20
10
2
6
MAX
5
20
30
-
-
-
10
150
-
0.01
-
0.01
45
45
15
3
-
UNITS
mV
pA
pA
kV/V
dB
dB
V
µV/V
V
V
V
V
mA
mA
mA
mA
µV/
o
C
Common-Mode Rejection Ratio
Common-Mode Input-Voltage Range
Power-Supply Rejection Ratio
Maximum Output Voltage
CMRR
V
lCR
PSRR
V
OM
+
V
OM
-
V
OM
+
V
OM
-
R
L
=
∞
∆V
IO
/∆V
S
, V
S
=
±7.5V
R
L
= 2kΩ
70
0
-
12
-
14.99
-
V
O
= 0V (Source)
V
O
= 15V (Sink)
V
O
= 7.5V, R
L
=
∞
V
O
= 0V, R
L
=
∞
12
12
-
-
-
Maximum Output Current
I
OM
+
I
OM
-
Supply Current (Note 3)
I+
Input Offset Voltage Temperature Drift
∆V
IO
/∆T
Electrical Specifications
PARAMETER
For Design Guidance, V
SUPPLY
=
±7.5V,
T
A
= 25
o
C, Unless Otherwise Specified
CA3160
SYMBOL
TEST CONDITIONS
10kΩ Across Terminals 4 and 5 or
Terminals 4 and 1
R
I
C
I
e
N
f = 1MHz
BW = 0.2MHz
R
S
= 1MΩ
R
S
= 10MΩ
TYP
±22
1.5
4.3
40
50
72
30
CA3160A
TYP
±22
1.5
4.3
40
50
72
30
UNITS
mV
TΩ
pF
µV
µV
nV/√Hz
nV/√Hz
Input Offset Voltage Adjustment Range
Input Resistance
Input Capacitance
Equivalent Input Noise Voltage
Equivalent Input Noise Voltage
e
N
R
S
= 100Ω
1kHz
10kHz
2
CA3160, CA3160A
Electrical Specifications
PARAMETER
Unity Gain Crossover Frequency
Slew Rate
Transient Response
Rise and Fall Time
Overshoot
Settling Time
For Design Guidance, V
SUPPLY
=
±7.5V,
T
A
= 25
o
C, Unless Otherwise Specified
(Continued)
CA3160
SYMBOL
f
T
SR
t
r
OS
t
S
C
L
= 25pF, R
L
= 2kΩ, (Voltage Follower)
To <0.1%, V
IN
= 4V
P-P
C
L
= 25pF, R
L
= 2kΩ, (Voltage Follower)
TEST CONDITIONS
TYP
4
10
0.09
10
1.8
CA3160A
TYP
4
10
0.09
10
1.8
UNITS
MHz
V/µs
µs
%
µs
Electrical Specifications
PARAMETER
Input Offset Voltage
Input Offset Current
Input Current
Common-Mode Rejection Ratio
Large Signal Voltage Gain
For Design Guidance, V+ = +5V, V- = 0V, T
A
= 25
o
C, Unless Otherwise Specified
CA3160
SYMBOL
V
IO
I
IO
I
l
CMRR
A
OL
V
O
= 4V
P-P
, R
L
= 5kΩ
TEST CONDITIONS
TYP
6
0.1
2
80
100
100
CA3160A
TYP
2
0.1
2
90
100
100
0 to 2.8
300
500
200
UNITS
mV
pA
pA
dB
kV/V
dB
V
µA
µA
µV/V
Common-Mode Input Voltage Range
Supply Current
V
lCR
I+
V
O
= 5V, R
L
=
∞
V
O
= 2.5V, R
L
=
∞
0 to 2.8
300
500
200
Power Supply Rejection Ratio
NOTE:
PSRR
∆V
IO
/∆V+
3. I
CC
typically increases by 1.5mA/MHz during operation.
Block Diagram
7
200µA
1.35mA
200µA
8mA
(NOTE 4)
0mA
(NOTE 5)
V+
NOTES:
4. Total supply voltage (for indicated voltage
gains) = 15V with input terminals biased so
that Terminal 6 potential is +7.5V above
Terminal 4.
5. Total supply voltage (for indicated voltage
gains) = 15V with output terminal driven to
either supply rail.
BIAS CKT.
+
3
INPUT
2
A
V
≈
5X
A
V
≈
6000X
A
V
≈
30X
OUTPUT
6
-
4
C
C
5
1
COMPENSATION
(WHEN DESIRED)
8
STROBE
V-
OFFSET
NULL
3
CA3160, CA3160A
Schematic Diagram
BIAS CURRENT
CURRENT SOURCE
FOR Q
6
AND Q
7
“CURRENT SOURCE
LOAD” FOR Q
11
Q
3
7
V+
Q
1
D
1
D
2
D
3
R
1
40kΩ
R
2
5kΩ
D
4
Q
2
Z
1
8.3V
Q
4
Q
5
INPUT STAGE
D
5
NON-INV.
INPUT
3
2
+
Q
6
D
6
D
7
SECOND
STAGE
OUTPUT
STAGE
Q
8
OUTPUT
6
Q
7
2kΩ
R
4
1kΩ
Q
10
30
pF
Q
11
Q
12
-
R
3
1kΩ
Q
9
INV. INPUT
R
5
1kΩ
R
6
1kΩ
5
OFFSET NULL
1
SUPPLEMENTARY
COMP IF DESIRED
8
STROBING
4
NOTE: Diodes D
5
Through D
7
Provide Gate Oxide Protection For MOSFET Input Stage.
Application Information
Circuit Description
Refer to the Block Diagram of the CA3160 series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3160 series circuits are
ideal for single supply operation. Three class A amplifier
stages, having the individual gain capability and current
consumption shown in the Block Diagram provide the total
gain of the CA3160. A biasing circuit provides two potentials
for common use in the first and second stages. Terminals 8
and 1 can be used to supplement the internal phase
compensation network if additional phase compensation or
frequency roll-off is desired. Terminals 8 and 4 can also be
used to strobe the output stage into a low quiescent current
state. When Terminal 8 is tied to the negative supply rail
(Terminal 4) by mechanical or electrical means, the output
potential at Terminal 6 essentially rises to the positive supply-
rail potential at Terminal 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load
resistance presented to the amplifier is very high (e.g., when
the amplifier output is used to drive MOS digital circuits in
comparator applications).
Input Stage
- The circuit of the CA3160 is shown in the
Schematic Diagram. It consists of a differential-input stage
using PMOS field-effect transistors (Q
6
, Q
7
) working into a
mirror-pair of bipolar transistors (Q
9
, Q
10
) functioning as load
resistors together with resistors R
3
through R
6
. The mirror-
pair transistors also function as a differential-to-single-ended
converter to provide base drive to the second-stage bipolar
transistor (Q
11
). Offset nulling, when desired, can be effected
by connecting a 100,000Ω potentiometer across Terminals 1
and 5 and the potentiometer slider arm to Terminal 4.
Cascode-connected PMOS transistors Q
2
, Q
4
, are the
constant-current source for the input stage. The biasing circuit
for the constant-current source is subsequently described.
The small diodes D
5
through D
7
provide gate-oxide protection
against high-voltage transients, including static electricity
during handling for Q
6
and Q
7
.
Second-Stage
- Most of the voltage gain in the CA3160 is
provided by the second amplifier stage, consisting of bipolar
4
CA3160, CA3160A
transistor Q
11
and its cascode-connected load resistance
provided by PMOS transistors Q
3
and Q
5
. The source of bias
potentials for these PMOS transistors is described later. Miller
Effect compensation (roll off) is accomplished by means of the
30pF capacitor and 2kΩ resistor connected between the base
and collector of transistor Q
11
. These internal components
provide sufficient compensation for unity gain operation in
most applications. However, additional compensation, if
desired, may be used between Terminals 1 and 8.
Bias-Source Circuit
- At total supply voltages, somewhat
above 8.3V, resistor R
2
and zener diode Z
1
serve to establish a
voltage of 8.3V across the series-connected circuit, consisting
of resistor R
1
, diodes D
1
through D
4
, and PMOS transistor Q
1
.
A tap at the junction of resistor R
1
and diode D
4
provides a
gate-bias potential of about 4.5V for PMOS transistors Q
4
and
Q
5
with respect to Terminal 7. A potential of about 2.2V is
developed across diode-connected PMOS transistor Q
1
with
respect to Terminal 7 to provide gate bias for PMOS transistors
Q
2
and Q
3
. It should be noted that Q
1
is “mirror-connected” to
both Q
2
and Q
3
. Since transistors Q
1
, Q
2
, Q
3
are designed to
be identical, the approximately 200µA current in Q
1
establishes
a similar current in Q
2
and Q
3
as constant-current sources for
both the first and second amplifier stages, respectively.
At total supply voltages somewhat less than 8.3V, zener diode
Z
1
becomes nonconductive and the potential, developed
across series-connected R
1
, D
1
- D
4
, and Q
1
, varies directly
with variations in supply voltage. Consequently, the gate bias
for Q
4
, Q
5
and Q
2
, Q
3
varies in accordance with supply-
voltage variations. This variation results in deterioration of the
power-supply-rejection ratio (PSRR) at total supply voltages
below 8.3V. Operation at total supply voltages below about
4.5V results in seriously degraded performance.
Output Stage
- The output stage consists of a drain-loaded
inverting amplifier using CMOS transistors operating in the
Class A mode. When operating into very high resistance loads,
the output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain is
dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 17. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be encountered.
As a voltage follower, the amplifier can achieve 0.01% accuracy
levels, including the negative supply rail.
Input Current Variation with Common Mode Input
Voltage
As shown in the Electrical Specifications, the input current for
the CA3160 Series Op Amps is typically 5pA at T
A
= 25
o
C
when Terminals 2 and 3 are at a common-mode potential of
+7.5V with respect to negative supply Terminal 4. Figure 23
contains data showing the variation of input current as a
function of common-mode input voltage at T
A
= 25
o
C. These
data show that circuit designers can advantageously exploit
these characteristics to design circuits which typically require
an input current of less than 1pA, provided the common-mode
input voltage does not exceed 2V. As previously noted, the
input current is essentially the result of the leakage current
through the gate-protection diodes in the input circuit and,
therefore, a function of the applied voltage. Although the finite
resistance of the glass terminal-to-case insulator of the metal
can package also contributes an increment of leakage current,
there are useful compensating factors. Because the gate-
protection network functions as if it is connected to Terminal 4
potential, and the metal can case of the CA3160 is also
internally tied to Terminal 4, input Terminal 3 is essentially
“guarded” from spurious leakage currents.
Input-Current Variation with Temperature
The input current of the CA3160 Series circuits is typically 5pA
at 25
o
C. The major portion of this input current is due to
leakage current through the gate-protective diodes in the input
circuit. As with any semiconductor junction device, including op
amps with a junction-FET input stage, the leakage current
approximately doubles for every 10
o
C increase in temperature.
Figure 24 provides data on the typical variation of input bias
current as a function of temperature in the CA3160.
In applications requiring the lowest practical input current and
incremental increases in current because of “warm-up” effects,
it is suggested that an appropriate heat sink be used with the
CA3160. In addition, when “sinking” or “sourcing” significant
output current the chip temperature increases, causing an
increase in the input current. In such cases, heat-sinking can
also very markedly reduce and stabilize input current variations.
Input Offset Voltage (V
IO
) Variation with DC Bias
vs Device Operating Life
It is well known that the characteristics of a MOSFET device
can change slightly when a DC gate-source bias potential is
applied to the device for extended time periods. The magnitude
of the change is increased at high temperatures. Users of the
CA3160 should be alert to the possible impacts of this effect if
the application of the device involves extended operation at
high temperatures with a significant differential DC bias voltage
applied across Terminals 2 and 3. Figure 25 shows typical data
pertinent to shifts in offset voltage encountered with CA3160
devices in metal can packages during life testing. At lower
temperatures (metal can and plastic) for example at 85
o
C, this
change in voltage is considerably less. In typical linear
applications where the differential voltage is small and
symmetrical, these incremental changes are of about the same
Offset Nulling
Offset-voltage nulling is usually accomplished with a
100,000Ω potentiometer connected across Terminals 1 and
5 and with the potentiometer slider arm connected to
Terminal 4. A fine offset-null adjustment usually can be
effected with the slider arm positioned in the mid-point of the
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