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74LVC374A-Q100
Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive
edge-trigger; 3-state
Rev. 1 — 22 November 2012
Product data sheet
1. General description
The 74LVC374A-Q100 is an octal D-type flip-flop featuring separate D-type inputs for
each flip-flop and 3-state outputs for bus-oriented applications. A clock input (CP) and an
outputs enable input (OE) are common to all flip-flops.
The eight flip-flops store the state of their individual D-inputs that meet the set-up and hold
times requirements on the LOW to HIGH CP transition.
When pin OE is LOW, the contents of the eight flip-flops is available at the outputs. When
pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE
input does not affect the state of the flip-flops.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs/outputs; for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74LVC374A-Q100
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC374AD-Q100
40 C
to +125
C
Name
SO20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
Version
SOT163-1
SOT360-1
SOT764-1
Type number
74LVC374APW-Q100
40 C
to +125
C
74LVC374ABQ-Q100
40 C
to +125
C
DHVQFN20 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads;
20 terminals; body 2.5
4.5
0.85 mm
4. Functional diagram
1
11
EN
C1
2
5
6
9
12
15
16
19
mna196
11
3
4
7
8
13
14
17
18
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
mna891
3
1D
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
4
7
8
13
14
17
18
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
2 of 18
NXP Semiconductors
74LVC374A-Q100
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
FF1
to
FF8
3-STATE
OUTPUTS
Q0
Q1
Q2
Q3
2
5
6
9
Q4 12
Q5 15
Q6 16
Q7 19
11 CP
1 OE
mna892
Fig 3.
Functional diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
FF1
FF2
FF3
FF4
FF5
FF6
FF7
FF8
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna893
Fig 4.
Logic diagram
74LVC374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
3 of 18
NXP Semiconductors
74LVC374A-Q100
Octal D-type flip-flop; 5 V tolerance; positive edge-trigger; 3-state
5. Pinning information
5.1 Pinning
/9&$4
WHUPLQDO
LQGH[ DUHD
9
&&
4
'
'
4
4
'
*1'
*1'
&3
'
4
2(
/9&$4
2(
4
'
'
4
4
'
'
4
9
&&
4
'
'
4
4
'
'
4
&3
DDD
4
'
'
4
4
'
'
4
*1'
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO20 and TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
1
11
D[0:7]
Q[0:7]
10
20
Pin description
Pin
OE
CP
3, 4, 7, 8, 13, 14, 17, 18
2, 5, 6, 9, 12, 15, 16, 19
GND
V
CC
Description
output enable input (active LOW)
clock input (LOW to HIGH, edge-triggered)
data input
3-state flip-flop output
ground (0 V)
supply voltage
74LVC374A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 22 November 2012
4 of 18
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