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SPL11A PROGRAMMING GUIDE

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SPL11A Programming Guide

V0.1 – Oct. 23, 2002

Technology for easy living

SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information

provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable.

TECHNOLOGY CO. makes no warranty for any errors which may appear in this document.

However, SUNPLUS

Contact SUNPLUS

TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order.

parties which may result from its use.

responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third

In addition, SUNPLUS products are not authorized for use as critical

components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the

product may reasonably be expected to result in significant injury to the user, without the express written approval

of Sunplus.

19, Innovation Road 1

•

Science-Based Industrial Park

•

Hsin-Chu

•

Taiwan

•

R.O.C.

886-3-578-6005

886-3-578-4418

fae@sunplus.com.tw

www.sunplus.com.tw

PRELIMINARY

SPL11A PROGRAMMING GUIDE

0 Table of Content

TABLE OF CONTENT ..................................................................................................................................... 2

REVISION HISTORY ....................................................................................................................................... 5

INTRODUCTION .............................................................................................................................................. 6

2.1 G

ENERAL

ESCRIPTION

............................................................................................................................ 6

2.2 F

EATURE

................................................................................................................................................. 6

2.3 A

PPLICATION

............................................................................................................................................ 7

2.4 S

TRUCTURE

IAGRAM

............................................................................................................................... 8

MEMORY ......................................................................................................................................................... 9

3.1 M

EMORY

APPING

................................................................................................................................... 9

3.2 M

EMORY LOCATION

................................................................................................................................. 10

3.3 V

ECTOR

................................................................................................................................................ 10

3.4 E

RROR

ADDRESS AREA

........................................................................................................................... 10

3.5 E

XAMPLE

............................................................................................................................................... 10

CPU CLOCK CONTROL ................................................................................................................................11

4.1 C

LOCK

OURCE

ONTROL

.......................................................................................................................11

4.1.1 Clock sources combination (OTP)..........................................................................................11

4.2 CPU C

LOCK

ONTROL

EGISTER

............................................................................................................11

4.2.1 P_05H_CPU_CLK ($0005):

set CPU clock

..........................................................................11

IO AND RFC FUNCTION ............................................................................................................................... 12

5.1 P

ORT

A(IOA) C

ONTROL

EGISTER

........................................................................................................... 12

5.1.1 P_00H_IOA_Data ($0000): Data register of PortA ................................................................ 12

5.1.2 P_01H_IOA_Dir ($0001): Direction Control register of PortA ................................................ 12

5.1.3 P_02H_IOA_Attrib ($0002): Attribute data register of PortA.................................................. 12

5.2 R

ESISTOR TO

REQUENCY

ONVERTER

(RFC) F

UNCTION

.......................................................................... 14

5.2.1 P_13H_RFC_CTL ($0013):

RFC Control Register

............................................................ 14

5.2.2 How to use RFC function....................................................................................................... 15

5.2.3 Function description of PortA(IOA[7:0])................................................................................. 15

5.2.4 IOA Structure......................................................................................................................... 16

5.3 P

ORT

B(INB) C

ONTROL

EGISTER

........................................................................................................... 18

5.3.1 P_03H_INB_Data ($0003)..................................................................................................... 18



Sunplus Technology Co., Ltd.

PAGE 2

V0.1 – OCT. 23, 2002

PRELIMINARY

SPL11A PROGRAMMING GUIDE

5.3.2 P_10H_IO_Config ($0010) .................................................................................................... 18

5.3.3 INB Structure......................................................................................................................... 19

SYSTEM CONTROL ...................................................................................................................................... 20

6.1 S

YSTEM

ONTROL

.................................................................................................................................. 20

6.1.1 P_0FH_SYS_SWITCH ($000F) ............................................................................................ 20

6.1.2 P_0FH_SYS_SWITCH ($000F) ............................................................................................ 21

6.2 R

ESET

LAGS

........................................................................................................................................ 22

6.2.1 P_12H_RST_FG ($0012) ...................................................................................................... 22

TIMER/COUNTER ......................................................................................................................................... 23

7.1 T

IMER

TRUCTURE

................................................................................................................................. 23

7.2 T

IMER

ETUP

& I

NITIALIZATION

................................................................................................................ 23

7.2.1 P_09H_TIMER_SET ($0009): Set the timer/counter configuration ....................................... 23

7.3 T

IMER

NTERRUPT

LOCK

OURCES

........................................................................................................ 24

A. HSCK sources for timer, interrupt ................................................................................................ 24

7.3.1 P_0CH_TIMER_INT1 ($000C) .............................................................................................. 24

LSCK(32768) sources for timer, interrupt sources ................................................................... 25

7.3.2 P_0DH_TIMER_INT2 ($000D) .............................................................................................. 25

7.4 T

IMER

ATA

EGISTER

............................................................................................................................ 26

7.4.1 P_0AH_TML_LATCH ($000A)............................................................................................... 26

7.4.2 P_0BH_TMH_LATCH ($000B) .............................................................................................. 26

LCD ................................................................................................................................................................ 27

8.1 LCD RAM

MAPPING

............................................................................................................................... 27

8.2 C

ONTROL REGISTERS

.............................................................................................................................. 27

8.2.1 Port_LCD_CTL ($0004)......................................................................................................... 27

8.2.2 LCD clock control .................................................................................................................. 29

8.3 M

ULTIPLE FUNCTIONS

(I/O,

SEGMENT

COMMON SHARING

) ....................................................................... 30

8.3.1 LCD dot & I/O ........................................................................................................................ 30

8.3.2 LCD mapping with dot resolution........................................................................................... 31

WAKEUP / INTERRUPT ................................................................................................................................ 32

9.1 W

AKEUP

NTERRUPT

TRUCTURE

IAGRAM

.............................................................................................. 32

9.2 W

AKEUP

NTERRUPT

ONTROL REGISTERS

............................................................................................... 33

9.2.1 P_07H_WKU_SET ($0007)................................................................................................... 33

9.2.2 Port_WKU_CLR ($0008) ....................................................................................................... 34

9.2.3 P_0EH_INT_SET($000E)...................................................................................................... 34



Sunplus Technology Co., Ltd.

PAGE 3

V0.1 – OCT. 23, 2002

PRELIMINARY

SPL11A PROGRAMMING GUIDE

10 REMOTE CONTROL ..................................................................................................................................... 36

10.1 R

EMOTE CONTROL MODULE DIAGRAM

........................................................................

錯誤! 尚未定義書籤。

10.2 C

ONTROL REGISTERS

.............................................................................................................................. 36

10.2.1 P_06H_DUTY_CTL ($0006).................................................................................................. 36

11 DEVELOPMENT SYSTEM ............................................................................................................................ 37

11.1 SPL11A S

IMULATOR

.............................................................................................................................. 37

11.2 OTP W

RITER AND DEMO BOARD

.............................................................................................................. 37

12 MASK/BONDING OPTION ............................................................................................................................ 39

12.1 M

ASK OPTIONS FOR

ROM

VERSION OF

SPL11A ....................................................................................... 39

12.2 B

ONDING OPTIONS FOR

OTP

VERSION OF

SPL11A ................................................................................... 39

12.3 D

EFAULT STATUS OF PINS

........................................................................................................................ 39

13 APPENDIX ..................................................................................................................................................... 40

13.1 P

ORT AND

EMORY

......................................................................................................................... 40

13.2 OTP (QFP) PIN D

ESCRIPTION

............................................................................................................... 41



Sunplus Technology Co., Ltd.

PAGE 4

V0.1 – OCT. 23, 2002

SPL11A

SPL11A概述

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