TLE 5226 G
Smart Quad Channel Low-Side Switch
Features
•
Low ON-resistance 2 x 0.2
Ω
, 2 x 0.35
Ω
(typ.)
•
Power - SO 20 - Package with integrated
cooling area
•
Overload shutdown
•
Selective thermal shutdown
•
Status monitoring
•
Overvoltage protection
•
Shorted circuit protection
•
Standby mode with low current consumption
•
µC compatible input
•
Electostatic discharge
(ESD) protection
Product Summary
Supply voltage
Drain source voltage
On resistance
Output current
V
S
V
DS(AZ)max
R
ON(typ) 1,2
R
ON(typ) 3,4
I
D 1,2
I
D 3,4
4.8 - 32
60
0.2
0.35
2x5
2x3
V
V
Ω
Ω
A
A
Application
•
All kinds of resistive and inductive loads (relays,electromagnetic valves)
•
µC compatible power switch for 12 and 24 V applications
•
Solenoid control switch in automotive and industrial control systems
P-DSO-20-10
General description
Quad channel Low-Side-Switch (2x5A/2x3A) in Smart Power Technology (SPT) with four seperate in-
puts and four open drain DMOS output stages. The TLE 5226 is fully protected by embedded protecti-
on functions and designed for automotive and industrial applications.
Pin Description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Symbol
GND
OUT1
ST1
IN4
VS
STBY
IN3
ST2
OUT2
GND
GND
OUT3
ST3
IN2
GND
ENA
IN1
ST4
OUT4
GND
Function
Ground
Power Output channel 1
Status Output channel 1
Control Input channel 4
Supply Voltage
Standby
Control Input channel 3
Status Output channel 2
Power Output channel 2
Ground
Ground
Power Output channel 3
Status Output channel 3
Control Input channel 2
Ground Logic
Enable Input for all four channels
Control Input channel 1
Status Output channel 4
Power Output channel 4
Ground
Pin Configuration (Top view)
P - DSO - 20 - 10
Semiconductor Group
Page
1
1998-02-04
TLE 5226 G
Block Diagram
VS
STBY
internal supply
ENA
Overtemperature
Channel 4
Overtemperature
Channel 1
Open Load
IN1
LOGIC
Overload
OUT1
RPD
ST1
Open Load
IN4
Overload
LOGIC
OUT4
RPD
ST4
Overtemperature
Channel 3
Overtemperature
Channel 2
Open Load
IN2
LOGIC
Overload
OUT2
RPD
ST2
Open Load
IN3
Overload
LOGIC
OUT3
RPD
ST3
GND
Semiconductor Group
Page
2
1998-02-04
TLE 5226 G
Block Diagram of Open Load Detection
Semiconductor Group
Page
3
1998-02-04
TLE 5226 G
Maximum Ratings for T
j
= – 40°C to 150°C
Parameter
Supply voltage
Supply voltage operational range
Continuous drain source voltage (OUT1...OUT4)
Input voltage IN1 to IN4, ENA
Input voltage STBY
Status output voltage
Operating temperature range
Storage temperature range
Output current per channel
Output current at reversal supply
Status output current
Inductive load switch off dissipation energy
Thermal resistance
junction - case
junction - ambient @ min. footprint
junction - ambient @ 6 cm
2
cooling area
T
j
= 25°C
Symbol
V
S
Values
-0.3 ... + 40
+ 4.8 ... + 32
40
- 0.3 ... + 6
- 0.3 ... + 40
- 0.3 ... + 32
- 40 ... + 150
- 55 ... + 150
self limited
-4
-2
- 5 ... + 5
50
4.5
50
40
V
°C
A
A
mA
mJ
K/W
Unit
V
V
V
V
V
S
V
DS
V
IN
,
V
ENA
V
STBY
V
ST
T
j
T
stg
I
D(lim)
I
D 1,2
I
D 3,4
I
ST
E
AS
R
thJC
R
thJA
Test board for
6 cm
2
cooling area
min. footprint
Semiconductor Group
Page
4
1998-02-04
TLE 5226 G
Electrical Characteristics
Parameter and Conditions
V
S
= 4.8 to 18 V ; T
j
= - 40 °C to + 150 °C
(unless otherwise specified)
1. Power Supply (V
S
)
Supply current (Outputs ON)
Supply current (Outputs OFF)
V
ENA
= L, V
STBY
= H
Operating voltage
Standby current
2. Power Outputs
ON state resistance Channel 1,2
I
D
= 1A; V
S
≥
9.5 V
ON state resistance Channel 3,4
I
D
= 1A; V
S
≥
9.5 V
Z-Diode clamping voltage (OUT1...4)
Pull down resistor
V
STBY
= H, V
IN
= L
Output leakage current
Output on delay time
2
Output off delay time
2
Output on fall time
2
Output off rise time
2
Output off status delay time
2
Output on status delay time
3
Overload switch-off delay time
3. Digital Inputs (IN1, IN2, IN3, IN4, ENA)
Input low voltage
Input high voltage
Input voltage hysteresis
3
Input pull down current
Enable pull down current
V
IN
= 5 V; V
S
≥
6.5 V
V
ENA
= 5 V; V
S
≥
6.5 V
T
j
= 25
°
C
T
j
= 125°C
1
T
j
= 25
°
C
1
T
j
= 125°C
I
D
≥
100 mA
V
STBY
= L
Symbol
Values
min
Unit
typ
max
I
S
I
S
V
S
I
S
4.8
8
4
32
10
mA
mA
V
µA
R
DS(ON)
R
DS(ON)
V
DS(AZ)
R
PD
I
Dlk
t
on
t
off
t
fall
t
rise
t
4
t
5
t
DSO
45
14
10
0.2
0.5
0.35
0.75
60
20
26
40
20
10
5
5
10
50
100
65
80
40
40
60
50
300
Ω
Ω
V
kΩ
µA
µs
T
j
= 25
°C
T
j
= -40 °C ...150°C
V
STBY
= L
I
D
= 1 A
I
D
= 1 A
I
D
= 1 A
I
D
= 1 A
I
D
= 1 A
V
INL
V
INH
V
INHys
I
IN
I
ENA
- 0.3
2.0
50
10
10
100
30
20
1.0
6.0
60
40
V
V
mV
µA
µA
4. Digital Status Outputs (ST1 - ST4) open Drain
Output voltage low
Leakage current high
I
ST
= 2 mA
V
STL
I
STH
0.5
10
V
µA
1
2
Measured on P-DSO-20 devices
See timing diagram, resitive load condition; V
S
≥
9 V
3
This parameter will not be tested but assured by design
Semiconductor Group
Page
5
1998-02-04
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