3-A DC Motor Driver
TLE 5204
Overview
Features
•
•
•
•
•
•
•
Output current
±
3 A
I/O
error diagnostics
Short-circuit proof
Four-quadrant operation
Integrated free-wheeling diodes
Wide temperature range
Break low
and
break high, if open load detection is
required, the device TLE 5203 will fit
SPT IC
1)
P-TO220-7-1
P-TO220-7-8
Type
TLE 5204
TLE 5204 G
Description
Ordering Code
Q67000-A9177
Q67006-A9234
Package
P-TO220-7-1
P-TO220-7-8
TLE 5204 is an integrated power bridge with DMOS output stages for driving DC motors.
This motor bridge is optimized for driving DC motors in reversible operation. The internal
protective circuitry in particular ensures that no crossover currents can occur.
Because the free-wheeling diodes are integrated, the external circuitry that is necessary
is reduced to the capacitors on the supply voltage.
The control inputs have TTL/CMOS-compatible levels.
1)
SIEMENS Power Technology
Semiconductor Group
1
1998-02-01
TLE 5204
TLE 5204
TLE 5204 G
1
2
3 4 5
6
7
EF
Q1
Ι
1
GND
Ι
2
V
S
Q2
AEP01224
Figure 1
Pin Configuration
(top view)
Pin Definitions and Functions
Pin No.
1
2
3
4
5
6
7
Symbol
Q1
EF
I1
GND
I2
Function
Output of channel 1;
Short-circuit proof, free-wheeling
diodes integrated for inductive loads
Error flag;
TTL/CMOS-compatible output for error detection
(open drain)
Control input 1;
TTL/CMOS-compatible
Ground;
connected internally to cooling fin
Control input 2;
TTL/CMOS-compatible
Supply voltage;
wire with capacitor matching load
Output of channel 2;
Short-circuit proof, free-wheeling
diodes integrated for inductive loads
V
S
Q2
Semiconductor Group
2
1998-02-01
TLE 5204
Circuit Description
Input Circuit
The control inputs consist of TTL/CMOS-compatible Schmitt triggers with hysteresis.
Buffer amplifiers are driven by these stages and convert the logic signal into the
necessary form for driving the power output stages.
Output Stages
The output stages form a switched H-bridge. Protective circuits make the outputs short-
circuit proof to ground and to the supply voltage throughout the operating range. Positive
and negative voltage spikes, which occur when switching inductive loads, are clamped
by integrated power diodes.
Functional Truth Table
E1
L
L
H
H
E2
L
H
L
H
Q1
L
L
H
H
Q2
L
H
L
H
Comments
Motor brake; both low side transistors turned-ON
Motor turns clockwise
Motor turns counterclockwise
Motor brake; both high side transistors turned-ON
Notes for Output Stage
Symbol
L
H
Value
Low side transistor is turned-ON
High side transistor is turned-OFF
High side transistor is turned-ON
Low side transistor is turned-OFF
Semiconductor Group
3
1998-02-01
TLE 5204
Monitoring Functions
An internal circuit ensures that all output transistors are turned-OFF if the supply voltage
is below the operating range.
A monitoring circuit for each output transistor detects whether the particular transistor is
active and in this case prevents the corresponding source transistor (sink transistor) from
conducting in sink operation (source operation). Therefore no crossover currents can
occur. Pulse-width operation is possible up to a maximum switching frequency of 1 kHz
for any load.
Depending on the load current higher frequencies are possible.
Protective Function
Various errors like short-circuit to +
V
S
, ground or across the load are detected. All faults
result in turn-OFF of the output stages after a delay of 40
µs
and setting of the error flag
EF to ground. Changing the inputs resets the error flag.
Output Shorted to Ground Detection
If a high side transistor is switched on and its output is shorted to ground, the output
current is limited to typ 8 A. After a delay of 40
µs
all outputs will be switched off and the
error flag EF is set to ground.
Output Shorted to +
V
S
and Overload Detection
An internal circuit detects if the current through the low side transistor is higher than 4 A
typ. In this case all outputs are turned-OFF after 40
µs
and the error flag is set to ground.
At a junction temperature higher than 160
°C
the thermal shutdown turns-OFF, all four
output stages commonly and the error flag is set without a delay.
Diagnosis
Input
E1
L
L
H
H
E2
L
H
L
H
Q1
L
L
H
H
Output
Q2
L
H
L
H
Shorted
to GND
–
Q2
Q1
Q1, Q2
Diagnosis
Shorted
to
V
S
Q1, Q2
Q1
Q2
–
Overload
–
X
X
–
L
L
L
L
EF
Semiconductor Group
4
1998-02-01
TLE 5204
Error Flag
2
Error
Flag
Protection
Circuit 1
V
S
6
Control Input 1
3
1
Output 1
Control Input 2
5
7
Output 2
Protection
Circuit 1
4
GND
AEB01225
Figure 2
Block Diagram
5
1998-02-01
Semiconductor Group
FPGA/CPLD
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