Dual Low-Drop Voltage Regulator
TLE 4470
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Stand-by output 180 mA; 5 V
±
2 %
Adjustable reset switching threshold
Main output 350 mA; tracked to the stand-by output
Low quiescent current consumption in standby mode
Disable function for main output
Wide operation range: up to 45 V
Very low dropout
Power-On-Reset circuit sensing the stand-by voltage
Early warning comparator for supply undervoltage
Output protected against short circuit
Wide temperature range: – 40
°C
to 150
°C
Over-temperature protection
Over-load protection
P-DSO-14-4
P-DSO-20-6
Type
TLE 4470 GS
TLE 4470 G
Functional Description
Ordering Code
Q67006-A9309
Q67006-A9308
Package
P-DSO-14-4 (SMD)
P-DSO-20-6 (SMD)
The TLE 4470 is a monolithic integrated voltage regulator with two very low-drop
outputs, a main output Q2 for loads up to 350 mA and a stand by output Q1 providing a
maximum of 180 mA. The device is available in both the P-DSO-14-4 and P-DSO-20-6
packages. It is designed to supply microprocessor systems under the severe conditions
of automotive applications and is therefore equipped with additional protection functions
against over load, short circuit and over temperature. Of course the TLE 4470 can also
be used in other applications where two stabilized voltages are required.
The device operates in the wide temperature range of – 40
°C
to 150
°C.
The stand by regulator transforms an input voltage
V
I
in the range of 5.6 V
≤
V
I
≤
45 V to
V
Q1rated
= 5 V within an accuracy of 2%, whereas the main regulator is adjustable. By use
of an external voltage divider the main output voltage can be set to
V
Q2
≥
5 V for the
Semiconductor Group
1
1998-11-01
TLE 4470
TLE 4470 G type (P-DSO-20-6 package).
V
Q1
is compared to the voltage at pin VA,
which is proportional to the output voltage
V
Q2
. A control amplifier drives the base of the
series PNP transistor via a buffer.
The main output voltage
V
Q2
is tracked to the accuracy of the stand by output.
For the TLE 4470 GS (P-DSO-14-4 package) the output voltage is fixed to 5 V.
To save energy e.g. in battery powered body electronic applications, the main regulator
can be switched off via the disable input, which causes the current consumption to drop
to 180
µA
typical.
Two additional features of the TLE 4470 are an early warning comparator (can be used
e.g. to monitor the supply voltage
V
I
) and reset generator with an adjustable reset delay
time. The TLE 4470 G (P-DSO-20-6 package) has in addition an adjustable reset
switching threshold. This feature is useful with microprocessors which guarantee a safe
operation down to voltages below the internally set reset threshold of 4.65 V typical.
Two functions are included in the reset generator, a power on reset and an under-voltage
reset. The power on reset feature is necessary for a defined start of the microprocessor
when switching on the application. The reset LOW signal is generated for a certain delay
time after the output voltage
V
Q1
of the regulator has surpassed the reset threshold. An
external delay capacitor sets the delay time. The under voltage reset circuit supervises
the stand-by output voltage. In case
V
Q1
falls below the reset switching threshold the
reset output is set LOW after a short reaction time. The reset LOW signal is generated
down to an output voltage
V
Q1
of 1 V.
Pin Configuration
(top view)
P-DSO-14-4
D
DIS
GND
GND
GND
RQ
SQ
1
2
3
4
5
6
7
14
13
12
11
10
9
8
SI
P-DSO-20-6
RADJ
D
DIS
GND
GND
GND
GND
RQ
SQ
Q1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SI
Ι
1
Ι
2
GND
GND
GND
GND
Q2
Q2
ADJ2
AEP02151
Ι
GND
GND
GND
Q2
Q1
AEP02152
Figure 1
Semiconductor Group
2
1998-11-01
TLE 4470
Pin Definitions and Functions
P-DSO-20-6
Pin No.
1
Symbol
RADJ
Function
Reset switching threshold adjust;
for setting the reset
switching threshold connect to a voltage divider from Q1 to
GND. If this input is connected to GND, the reset is
triggered at the internal threshold.
Reset delay;
connect a capacitor
C
D
to GND for delay time
adjustment
Disable input main regulator;
Q2 disabled with high signal
Ground
Reset output;
the open collector output is connected to Q1
via an integrated 30 kΩ resistor
Sense output;
the open collector output is connected to Q1
via an integrated 30 kΩ resistor
Stand-by regulator output voltage;
block to GND with a
capacitor
C
Q1
≥
6
µF,
ESR < 10
Ω
at 10 kHz
Main regulator adjust input;
Q2 can be set to higher
values by an external divider
Main regulator output voltage;
block to GND with a
capacitor
C
Q2
≥
10
µF,
ESR < 10
Ω
at 10 kHz
Ground
Main regulator input voltage;
block to GND directly at the
IC with a ceramic capacitor
Stand-by regulator input voltage;
block to GND directly at
the IC with a ceramic capacitor
Sense comparator input
2
3
4, 5, 6, 7
8
9
10
11
12, 13
14, 15, 16, 17
18
19
20
D
DIS
GND
RQ
SQ
Q1
ADJ2
Q2
GND
I2
I1
SI
Semiconductor Group
3
1998-11-01
TLE 4470
P-DSO-14-4
Pin No.
1
2
3, 4, 5
6
7
8
9
Symbol
D
DIS
GND
RQ
SQ
Q1
Q2
Function
Reset delay;
connect a capacitor
C
D
to GND for delay time
adjustment
Disable input main regulator;
Q2 disabled with high signal
Ground
Reset output;
the open collector output is connected to Q1
via an integrated 30 kΩ resistor
Sense output;
the open collector output is connected to Q1
via an integrated 30 kΩ resistor
Stand-by regulator output voltage;
block to GND with a
capacitor,
C
Q1
≥
6
µF,
ESR < 10
Ω
at 10 kHz
Main regulator output voltage;
5 V output tracking to Q1,
block to GND with a capacitor
C
Q2
≥
10
µF,
ESR < 10
Ω
at
10 kHz
Ground
Main and stand-by regulator input voltage;
block to GND
directly at the IC with a ceramic capacitor
Sense comparator input
10, 11, 12
13
14
RADJ
ADJ2
GND
I
SI
Reset switching threshold adjust not available in P-DSO-14-4 package. Reset
is always triggered at the internal threshold.
Main regulator adjust input is internally connected to
V
Q2
Semiconductor Group
4
1998-11-01
TLE 4470
Ι
1
19
10
Q1
Reference
18
3
Stand-by-Regulator
12,
13
11
Ι
2
DIS
V
REF
Q2
ADJ2
Main Regulator
V
REF
2
Ι
d
8
30 k
Ω
V
Q1
1
30 k
Ω
9
D
RQ
=
V
RADJTH
Reset
RADJ
SQ
SI
20
=
Sense
4-7
14-17 GND
V
SITH
Pin numbers valid for P-DSO-20-6 (TLE 4470 G)
AEB02153
Figure 2
Block Diagram
Semiconductor Group
5
1998-11-01
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