BTS 716G
Smart High-Side Power Switch
Four Channels: 4 x 140mΩ
Status Feedback
Product Summary
Operating Voltage
V
bb
Active channels
On-state Resistance
R
ON
Nominal load current
I
L(NOM)
Current limitation
I
L(SCr)
5.5 ...40V
one
four parallel
140mΩ
35mΩ
2.6A
5.3A
6.5A
6.5A
Package
P-DSO-20
General Description
•
•
N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input and
diagnostic feedback, monolithically integrated in Smart SIPMOS technology.
Providing embedded protective functions
Applications
•
•
•
•
µC compatible high-side power switch with diagnostic feedback for 12V and 24V grounded loads
All types of resistive, inductive and capacitve loads
Most suitable for loads with high inrush currents, so as lamps
Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
•
•
•
•
•
•
•
Very low standby current
CMOS compatible input
Improved electromagnetic compatibility (EMC)
Fast demagnetization of inductive loads
Stable behaviour at undervoltage
Wide operating voltage range
Logic ground independent from load ground
Protection Functions
•
•
•
•
•
•
•
•
Short circuit protection
Overload protection
Current limitation
Thermal shutdown
Overvoltage protection (including load dump) with external
resistor
Reverse battery protection with external resistor
Loss of ground and loss of V
bb
protection
Electrostatic discharge protection (ESD)
Block Diagram
Vbb
IN1
ST1/2
IN2
Logic
Channel 1
Channel 2
Load 1
Load 2
Diagnostic Function
•
•
•
Diagnostic feedback with open drain output
Open load detection in OFF-state
Feedback of thermal shutdown in ON-state
IN3
ST3/4
IN4
Logic
Channel 3
Channel 4
Load 3
GND
Load 4
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2003-Oct-01
BTS 716G
Functional diagram
overvoltage
protection
internal
voltage supply
IN1
logic
gate
control
+
charge
pump
current limit
VBB
clamp for
inductive load
OUT1
ESD
temperature
sensor
Open load
detection
reverse
battery
protection
LOAD
.
ST1/2
channel 1
IN2
control and protection circuit
of
channel 2
OUT2
GND1/2
IN3
control and protection circuit
of
channel 3
OUT3
ST3/4
IN4
control and protection circuit
of
channel 4
OUT4
GND3/4
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BTS 716G
Pin Definitions and Functions
Pin
1,10,
11,12,
15,16,
19,20
3
5
7
9
18
17
14
13
4
8
2
6
Symbol Function
V
bb
Positive power supply voltage.
Design the
wiring for the simultaneous max. short circuit
currents from channel 1 to 2 and also for low
thermal resistance
IN1
Input 1,2,3,4
activates channel 1,2,3,4 in case
of logic high signal
IN2
IN3
IN4
OUT1
Output 1,2,3,4
protected high-side power output
of channel 1,2,3,4. Design the wiring for the
OUT2
max. short circuit current
OUT3
OUT4
ST1/2
Diagnostic feedback 1/2,3/4
of channel 1,2,3,4
ST3/4
open drain, low on failure
GND1/2
Ground
of chip 1 (channel 1,2)
GND3/4
Ground
of chip 2 (channel 3,4)
Pin configuration
(top view)
V
bb
GND1/2
IN1
ST1/2
IN2
GND3/4
IN3
ST3/4
IN4
V
bb
1
2
3
4
5
6
7
8
9
10
•
20
19
18
17
16
15
14
13
12
11
V
bb
V
bb
OUT1
OUT2
V
bb
V
bb
OUT3
OUT4
V
bb
V
bb
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BTS 716G
Maximum Ratings
at
T
j
= 25°C unless otherwise specified
Parameter
Supply voltage (overvoltage protection see page 6)
Supply voltage for full short circuit protection
T
j,start
= -40 ...+150°C
Load current (Short-circuit current, see page 6)
Load dump protection
1
)
V
LoadDump
=
V
A
+
V
s
,
V
A
= 13.5 V
R
I
2
)
= 2
Ω,
t
d
= 400 ms; IN = low or high,
each channel loaded with
R
L
= 13.5
Ω,
Operating temperature range
Storage temperature range
Power dissipation (DC)
4)
T
a
= 25°C:
T
a
= 85°C:
(all channels active)
Maximal switchable inductance, single pulse
V
bb
= 12V,
T
j,start
= 150°C
4)
,
see diagrams on page 10
I
L
= 2.3 A,
E
AS
= 76 mJ, 0
Ω
one channel:
I
L
= 3.3 A,
E
AS
= 182 mJ, 0
Ω
two parallel channels:
I
L
= 4.7 A,
E
AS
= 460 mJ, 0
Ω
four parallel channels:
Electrostatic discharge capability (ESD)
IN:
(Human Body Model)
ST:
out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993
R=1.5kΩ; C=100pF
Symbol
V
bb
V
bb
I
L
V
Load dump3
)
T
j
T
stg
P
tot
Values
43
36
self-limited
60
-40 ...+150
-55 ...+150
3.6
1.9
Unit
V
V
A
V
°C
W
Z
L
21
25
30
1.0
4.0
8.0
-10 ... +16
±0.3
±5.0
±5.0
mH
V
ESD
kV
Input voltage (DC)
see internal circuit diagram page 9
Current through input pin (DC)
Pulsed current through input pin
5
)
Current through status pin (DC)
V
IN
I
IN
I
IN
I
ST
V
mA
1
)
2)
3)
4
)
5
)
Supply voltages higher than V
bb(AZ)
require an external current limit for the GND and status pins (a 150Ω
resistor for the GND connection is recommended.
R
I
= internal resistance of the load dump test pulse generator
V
Load dump
is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
only for testing
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BTS 716G
Thermal Characteristics
Parameter and Conditions
Thermal resistance
junction - soldering point
6)7)
junction – ambient
6)
2
@ 6 cm cooling area
Symbol
Values
min
typ
max
--
--
--
--
--
--
44
35
17
--
--
--
Unit
each channel:
R
thjs
R
thja
one channel active:
all channels active:
K/W
Electrical Characteristics
Parameter and Conditions,
each of the four channels
at T
j
= -40...+150°C,
V
bb
= 12 V unless otherwise specified
Symbol
Values
min
typ
max
Unit
Load Switching Capabilities and Characteristics
On-state resistance (Vbb to OUT);
IL = 2 A
each channel,
T
j
= 25°C:
R
ON
T
j
= 150°C:
two parallel channels,
T
j
= 25°C:
four parallel channels,
T
j
= 25°C:
see diagram, page 11
--
--
--
--
2.3
3.3
4.7
--
110
210
55
28
2.6
3.7
5.3
--
140
280
70
35
--
--
--
2
mΩ
Nominal load current
one channel active:
I
L(NOM)
two parallel channels active:
four parallel channels active:
A
Device on PCB
6)
,
T
a
=
85°C,
T
j
≤
150°C
Output current
while GND disconnected or pulled up
8
)
;
I
L(GNDhigh)
Vbb = 32 V,
V
IN = 0,
see diagram page 9
Turn-on time
9
)
mA
µs
Turn-off time
R
L
= 12
Ω
Slew rate on
9
)
Slew rate off
9
)
IN
IN
to 90%
V
OUT
:
t
on
to 10%
V
OUT
:
t
off
--
--
0.2
0.2
100
100
--
--
250
270
1.0
1.1
10 to 30%
V
OUT
,
R
L
= 12
Ω:
dV/dt
on
70 to 40%
V
OUT
,
R
L
= 12
Ω:
-dV/dt
off
V/µs
V/µs
6
)
7
)
8
)
9
)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm
2
(one layer, 70µm thick) copper area for Vbb
connection. PCB is vertical without blown air. See page 14
Soldering point: upper side of solder edge of device pin 15. See page 14
not subject to production test, specified by design
See timing diagram on page 12.
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2003-Oct-01
FPGA/CPLD
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