1 M
×
1-Bit Dynamic RAM
Low Power 1 M
×
1-Bit Dynamic RAM
HYB 511000BJ-50/-60/-70
HYB 511000BJL-50/-60/-70
Advanced Information
1 048 576 words by 1-bit organization
Fast access and cycle time
50 ns access time
95 ns cycle time (-50 version)
60 ns access time
130 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
•
Fast page mode cycle time
35 ns (-50 version)
40 ns (-60 version)
45 ns (-70 version)
•
Low power dissipation
max. 495 mW active (-50 version)
max. 440 mW active (-60 version)
max. 385 mW active (-70 version)
max. 5.5 mW standby
max. 1.1 mW standby for L-version
•
•
•
•
•
•
•
•
•
Single + 5 V (± 10 %) supply with a built-in
V
BB
generator
Output unlatched at cycle end allows two-
dimensional chip selection
Common I/O capability using “early write”
operation
Read-modify-write, CAS-before-RAS
refresh, RAS-only refresh, hidden-refresh,
fast page mode capability and test mode
capability
All inputs, outputs and clocks
TTL-compatible
512 refresh cycles/8 ms
512 refresh cycles/64 ms
for L-version only
Plastic Packages:
P-SOJ-26/20-1
Ordering Information
Type
HYB 511000BJ-50
HYB 511000BJ-60
HYB 511000BJ-70
HYB 511000BJL-50
HYB 511000BJL-60
HYB 511000BJL-70
Ordering Code
Q67100-Q1056
Q67100-Q518
Q67100-Q519
on request
Q67100-Q526
Q67100-Q527
Package
P-SOJ-26/20-1
P-SOJ-26/20-1
P-SOJ-26/20-1
P-SOJ-26/20-1
P-SOJ-26/20-1
P-SOJ-26/20-1
Description
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
DRAM (access time 50 ns)
DRAM (access time 60 ns)
DRAM (access time 70 ns)
Semiconductor Group
33
01.95
HYB 511000BJ/BJL-50/-60/-70
1 M
×
1-DRAM
The HYB 511000BJ/BJL is the new generation dynamic RAM organized as 1 048 576 words by
1-bit. The HYB 511000BJ/BJL utilizes CMOS silicon gate process technology as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 511000BJ/BJL to be packaged in a standard plastic
P-SOJ-26/20. This package size provides high system bit densities and is compatible with
commonly used automatic testing and insertion equipment. System oriented features include single
+ 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as
Schottky TTL. “Test Mode” function is implemented. The HYB 511000BJL are specially selected for
low power battery backup applications.
Pin Definitions and Functions
Pin No.
A0-A9
RAS
DI
DO
CAS
WE
Function
Address Inputs
Row Address Strobe
Data In
Data Out
Column Address Strobe
Read/Write Input
Power Supply (+ 5 V)
Ground (0 V)
Test Function
No Connection
V
CC
V
SS
TF
N.C.
Semiconductor Group
34
HYB 511000BJ/BJL-50/-60/-70
1 M
×
1-DRAM
Pin Configuration
(top view)
SOJ-26/20-1
Semiconductor Group
35
HYB 511000BJ/BJL-50/-60/-70
1 M
×
1-DRAM
Block Diagram
Semiconductor Group
36
HYB 511000BJ/BJL-50/-60/-70
1 M
×
1-DRAM
Absolute Maximum Ratings
Operating temperature range .........................................................................................0 to + 70 ˚C
Storage temperature range......................................................................................– 55 to + 150 ˚C
Soldering temperature ............................................................................................................260 ˚C
Soldering time .............................................................................................................................10 s
Input/output voltage ........................................................................................................ – 1 to + 7 V
Test Function Input voltage ....................................................................................... – 1 to + 10.5 V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation..................................................................................................................... 0.6 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 ˚C;
V
SS
= 0 V;
V
CC
= 5 V
±
10 %
Parameter
Input high voltage
Input low voltage
Test enable input high voltage
Test disable input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current, any input except TF
(0 V
≤
V
IN
≤
6.5 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
5.5 V)
Average
V
CC
supply current:
-50 version
-60 version
-70 version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
Symbol
Limit Values
min.
max.
6.5
0.8
2.4
– 1.0
– 1.0
2.4
–
– 10
– 10
Unit Test
Condition
V
V
V
V
V
µA
µA
1)
1)
1)
1)
1)
1)
1)
V
IH
V
IL
V
IH(TF)
V
IL(TF)
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
V
CC
+ 4.5 10.5
–
0.4
10
10
V
CC
+ 1.0 V
1)
–
–
–
–
90
80
70
2
mA
mA
mA
mA
2) 3)
2) 3)
2) 3)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
–
Semiconductor Group
37
单片机
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