1M x 16-Bit Dynamic RAM
(1k-Refresh)
HYB5118160BSJ-50/-60/-70
Advanced Information
•
•
•
1 048 576 words by 16-bit organization
0 to 70 °C operating temperature
Performance:
-50
tRAC
tCAC
tAA
tRC
tPC
RAS access time
CAS access time
Access time from address
Read/Write cycle time
Fast page mode cycle time
50
13
25
90
35
-60
60
15
30
110
40
-70
70
20
35
130
45
ns
ns
ns
ns
ns
•
•
Single + 5 V (± 10 %) supply
Low power dissipation
max. 1100 active mW (-50 version)
max. 990 active mW (-60 version)
max. 880 active mW (-70 version)
11 mW standby (TTL)
5.5. mW standby (MOS)
Output unlatched at cycle end allows two-dimensional chip selection
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
self refresh
Fast page mode capability
2 CAS / 1 WE
All inputs, outputs and clocks fully TTL-compatible
1024 refresh cycles / 16 ms
Plastic Package:
P-SOJ-42-1 400 mil
•
•
•
•
•
•
•
Semiconductor Group
1
1.96
HYB 5118160BSJ-50/-60/-70
1M x 16-DRAM
The HYB 5118160BSJ is a 16 MBit dynamic RAM organized as 1 048 576 words by 16 bits. The
HYB 5118160BSJ utilizes a submicron CMOS silicon gate process technology, as well as advanced
circuit techniques to provide wide operating margins, both internally and for the system user.
Multiplexed address inputs permit the HYB 5118160BSJ to be packaged in a standard SOJ 42
400 mil plastic package. These packages provide high system bit densities and are compatible with
commonly used automatic testing and insertion equipment. System-oriented features include single
+ 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as
Schottky TTL.
Ordering Information
Type
HYB 5118160BSJ-50
HYB 5118160BSJ-60
HYB 5118160BSJ-70
Pin Names
A0 to A9
A0 to A9
RAS
OE
I/O1-I/O16
UCAS
LCAS
WE
Row Address Inputs
Column Addess Inputs
Row Address Strobe
Output Enable
Data Input/Output
Upper Column Address Strobe
Lower Column Address Strobe
Read/Write Input
Power Supply (+ 5 V)
Ground (0 V)
not connected
Ordering Code
Q67100-Q1072
Q67100-Q1073
Q67100-Q1074
Package
Descriptions
P-SOJ-42-1 400 mil DRAM (access time 50 ns)
P-SOJ-42-1 400 mil DRAM (access time 60 ns)
P-SOJ-42-1 400 mil DRAM (access time 70 ns)
V
CC
V
SS
N.C.
Semiconductor Group
2
HYB 5118160BSJ-50/-60/-70
1M x 16-DRAM
P-SOJ-42 (400 mil)
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
N.C.
N.C.
WE
RAS
N.C.
N.C.
A0
A1
A2
A3
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
N.C.
LCAS
UCAS
OE
A9
A8
A7
A6
A5
A4
Vss
Pin Configuration
Truth Table
RAS
H
L
L
L
L
L
L
L
L
LCAS
H
H
L
H
L
L
H
L
L
UCAS
H
H
H
L
L
H
L
L
L
WE
H
H
H
H
H
L
L
L
H
OE
H
H
L
L
L
H
H
H
H
I/O1-I/O8
High-Z
High-Z
Dout
High-Z
Dout
Din
Don't care
Din
High-Z
I/O9-I/O16
High-Z
High-Z
High-Z
Dout
Dout
Don't care
Din
Din
High-Z
Operation
Standby
Refresh
Lower byte read
Upper byte read
Word read
Lower byte write
Upper byte write
Word write
NOP
Semiconductor Group
3
HYB 5118160BSJ-50/-60/-70
1M x 16-DRAM
I/O1
I
/O2
I
/O16
WE
UCAS
LCAS
.
.
&
Data in
Buffer
No. 2 Clock
Generator
16
Data out
Buffer
16
OE
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Column
Address
Buffer(10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
16
Refresh
Counter (10)
10
Row
10
1024
x16
Address
Buffers(10)
10
Decoder
1024
Row
Memory Array
1024x1024x16
RAS
No. 1 Clock
Generator
Voltage Down
Generator
VCC
VCC (internal)
Block Diagram
Semiconductor Group
4
HYB 5118160BSJ-50/-60/-70
1M x 16-DRAM
Absolute Maximum Ratings
Operating temperature range ............................................................................................0 to 70 °C
Storage temperature range.........................................................................................– 55 to 150 °C
Input/output voltage ................................................................................-0.5 to min (Vcc+0.5,7.0) V
Power supply voltage...................................................................................................-1.0V to 7.0 V
Power dissipation..................................................................................................................... 1.0 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of
the device. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 5 V
±
10 %,
t
T
= 5 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current,any input
(0 V
≤
V
IH
≤
Vcc + 0.3V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
Vcc + 0.3V)
Average
V
CC
supply current:
-50 ns version
-60 ns version
-70 ns version
(RAS, CAS, address cycling,
t
RC
=
t
RC
min.
)
Symbol
Limit Values
min.
max.
Vcc+0.5
0.8
–
0.4
10
10
2.4
– 0.5
2.4
–
– 10
– 10
Unit Test
Condition
V
V
V
V
µA
µA
1)
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
–
–
–
200
180
160
mA
mA
mA
2) 3) 4)
2) 3) 4)
2) 3) 4)
Standby
V
CC
supply current (RAS = CAS =
V
IH
)
I
CC2
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
-70 ns version
(RAS cycling: CAS =
V
IH
,
t
RC
=
t
RC
min.
)
Semiconductor Group
5
–
–
–
–
2
200
180
160
mA
mA
mA
mA
–
2) 4)
2) 4)
2) 4)
I
CC3
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