4M
×
4-Bit Dynamic RAM
2k & 4k Refresh
(Fast Page Mode)
Advanced Information
• 4 194 304 words by 4-bit organization
• 0 to 70
°C
operating temperature
• Fast Page Mode operation
• Performance:
-50
-60
60
15
30
40
ns
ns
ns
ns
HYB 5116400BJ-50/-60
HYB 5117400BJ-50/-60
HYB 3116400BJ/BT-50/-60
HYB 3117400BJ-50/-60
t
RAC
RAS access time
t
CAC
CAS access time
t
AA
t
RC
t
PC
Access time from address
Read/Write cycle time
Fast page mode cycle time
50
13
25
84
35
104 ns
• Power Dissipation, Refresh & Addressing:
HYB 5116400
-50
Power Supply
Addressing
Refresh
Active
TTL Standby
CMOS Standby
275
11
5.5
-60
5 V
±
10%
12/10
220
HYB 3116400
-50
-60
3.3 V
±
0.3 V
12/10
180
7.2
3.6
144
HYB 5117400
-50
-60
5 V
±
10%
11/11
440
11
5.5
385
HYB 3117400
-50
-60
3.3 V
±
0.3 V
11/11
288
7.2
3.6
252
mW
mW
mW
4096 cycles / 64 ms
2048 cycles / 32 ms
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
• All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
• Plastic Package: P-SOJ-26/24-1
300 mil
P-TSOPII-26/24-1 300 mil
Semiconductor Group
1
1998-10-01
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M
×
4 DRAM
The HYB 5(3)116(7)400 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized
as 4 194 304 words by 4-bits. The HYB 5(3)116(7)400BJ/BT utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)400
to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment.
Ordering Information
Type
2k-Refresh Versions
HYB 5117400BJ-50
HYB 5117400BJ-60
HYB 3117400BJ-50
HYB 3117400BJ-60
4k-Refresh Versions
HYB 5116400BJ-50
HYB 5116400BJ-60
HYB 3116400BJ-50
HYB 3116400BJ-60
HYB 3116400BT-50
HYB 3116400BT-60
Q67100-Q1049
Q67100-Q1050
on request
on request
on request
on request
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
5 V 50 ns FPM-DRAM
5 V 60 ns FPM-DRAM
3.3 V 50 ns FPM-DRAM
3.3 V 60 ns FPM-DRAM
3.3 V 50 ns FPM-DRAM
3.3 V 60 ns FPM-DRAM
Q67100-Q1086
Q67100-Q1087
on request
on request
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
P-SOJ-26/24-1 300 mil
5 V 50 ns FPM-DRAM
5 V 60 ns FPM-DRAM
3.3 V 50 ns FPM-DRAM
3.3 V 60 ns FPM-DRAM
Ordering Code
Package
Descriptions
Semiconductor Group
2
1998-10-01
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M
×
4 DRAM
Pin Names
HYB 5(3)116400
4k-Refresh
Row Address Inputs
Column Address Inputs
Row Address Strobe
Column Address Strobe
Output Enable
Data Input/Output
Read/Write Input
Power Supply
Ground (0 V)
Not Connected
Pin Configuration
P-SOJ-26/24-1 300 mil
P-TSOPII-26/24-1 300 mil
–
A0 - A11
A0 - A9
HYB 5(3)117400
2k-Refresh
A0 - A10
A0 - A10
RAS
CAS
OE
I/O1 - I/O4
WE
V
CC
V
SS
N.C.
V
CC
I/O1
I/O2
WE
RAS
A11 / N.C.
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
SPP03454
V
SS
I/O4
I/O3
CAS
OE
A9
A8
A7
A6
A5
A4
V
SS
Semiconductor Group
3
1998-10-01
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M
×
4 DRAM
I/O1 I/O2 I/O3 I/O4
Data IN
Buffer
WE
CAS
4
No.2 Clock
Generator
&
Data OUT
Buffer
OE
4
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
Column
Address
Buffers (10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
4
Refresh
Counter (12)
12
12
Row
Address
Buffers (12)
12
Row
Decoder
4096
1024
x4
Memory Array
4096 x 1024 x 4
RAS
No.1 Clock
Generator
Voltage Down
Generator
SPB03455
V
CC
V
CC
(internal)
Block Diagram for HYB 5(3)116400 (4k-refresh)
Semiconductor Group
4
1998-10-01
HYB 5116(7)400BJ-50/-60
HYB 3116(7)400BJ/BT-50/-60
4M
×
4 DRAM
I/O1 I/O2 I/O3 I/O4
Data In
Buffer
WE
CAS
&
4
Data Out
Buffer
4
OE
No.2 Clock
Generator
11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
11
Column
Address
Buffers (11)
11
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
2048
x4
4
Refresh
Counter (11)
11
Row
Address
Buffers (11)
11
Row
Decoder
.
.
.
2048
.
.
.
Memory Array
2048 x 2048 x 4
.
.
.
.
.
.
RAS
No.1 Clock
Generator
Voltage Down
Generator
V
CC
V
CC
(internal)
SPB02823
Block Diagram for HYB 5(3)117400 (2k-refresh)
Semiconductor Group
5
1998-10-01
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