2M
x
32-Bit Dynamic RAM Module
HYM 322030S/GS-50/-60/-70
Advanced Information
•
•
•
2 097 152 words by 32-bit organization
1 memory bank
Fast access and cycle time
50 ns access time
90 ns cycle time (-50 version)
60 ns access time
110 ns cycle time (-60 version)
70 ns access time
130 ns cycle time (-70 version)
Fast page mode capability
35 ns cycle time (-50 version)
40 ns cycle time (-60 version)
45 ns cycle time (-70 version)
Single + 5 V (± 10 %) supply
Low power dissipation
max. 2640 mW active (-50 version)
max. 2420 mW active (-60 version)
max. 2200 mW active (-70 version)
CMOS – 22 mW standby
TTL
–44 mW standby
CAS-before-RAS refresh
RAS-only-refresh
Hidden-refresh
4 decoupling capacitors mounted on substrate
All inputs, outputs and clocks fully TTL compatible
72 pin Single in-Line Memory Module (L-SIM-72-9 ) with 20.32 mm (800 mil) height
Utilizes four 2M
×
8 -DRAMs in 400 mil SOJ packages
2048 refresh cycles / 32 ms with 11/10 addressing
Optimized for use in byte-write non-parity applications
Tin-Lead contact pads (S-version)
Gold contact pads (GS - version)
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Semiconductor
Semicunductor Group
1
9.95
HYM 322030S/GS-50/-60/-70
2M
×
32-Bit
The HYM 322030S/GS-50/-60/-70 is a 8 MByte DRAM module organized as 2 097 152 words by
32-bit in a 72-pin single-in-line package comprising four HYB 5117800BSJ 2M
×
8 DRAMs in 400
mil wide SOJ-packages mounted together with four 0.2
µF
ceramic decoupling capacitors on a PC
board.
Each HYB 5117800BSJ is described in the data sheet and is fully electrical tested and processed
according to SIEMENS standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use of four presence detect pins.
The common I/O feature on the HYM 322030S/GS-60/-70 dictates the use of early write cycles.
Ordering Information
Type
HYM 322030S-50
HYM 322030S-60
HYM 322030S-70
HYM 322030GS-50
HYM 322030GS-60
HYM 322030GS-70
Ordering Code
on request
Q67100-Q976
Q67100-Q977
on request
Q67100-Q2018
Q67100-Q2019
Package
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
L-SIM-72-9
Description
DRAM Module
(access time 50 ns)
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
DRAM Module
(access time 50 ns)
DRAM Module
(access time 60 ns)
DRAM Module
(access time 70 ns)
Semiconductor Group
2
HYM 322030S/GS-50/-60/-70
2M
×
32-Bit
Pin Configuration
Pin Names
VSS
DQ16
DQ17
DQ18
DQ19
N.C.
A1
A3
A5
A10
DQ20
DQ21
DQ22
DQ23
N.C.
A8
N.C.
N.C.
N.C.
VSS
CAS2
CAS1
N.C.
WE
DQ8
DQ9
DQ10
DQ11
DQ12
VCC
DQ13
DQ14
DQ15
PD0
PD2
N.C.
1 DQ0 2
3 DQ1 4
5 DQ2 6
7 DQ3 8
9 VCC 10
11 A0
12
13 A2
14
15 A4 16
17 A6 18
19 DQ4 20
21 DQ5 22
23 DQ6 24
25 DQ7 26
27 A7
28
29 VCC 30
31 A9
32
33 RAS2 34
35 N.C. 36
37 N.C. 38
39 CAS0 40
41 CAS3 42
43 RAS0 44
45 N.C. 46
47 N.C. 48
49 DQ24 50
51 DQ25 52
53 DQ26 54
55 DQ27 56
57 DQ28 58
59 DQ29 60
61 DQ30 62
63 DQ31 64
65 N.C. 66
67 PD1 68
69 PD3 70
71 VSS 72
A0R-A10R
A0C-A9C
DQ0-DQ31
CAS0 - CAS3
RAS0, RAS2
WE
Row Address Inputs
Column Address Inputs
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
Ground
Presence Detect Pin
No Connection
V
CC
V
SS
PD
N.C.
Presence Detect Pins
-50
PD0
PD1
PD2
PD3
N.C.
N.C.
-60
N.C.
N.C.
N.C.
N.C.
-70
N.C.
N.C.
V
SS
V
SS
V
SS
N.C.
Semiconductor Group
3
HYM 322030S/GS-50/-60/-70
2M
×
32-Bit
RAS0
CAS0
CAS
DQ0-DQ7
I/O1-I/O8
OE
D1
RAS
CAS1
CAS
DQ8-DQ15
I/O1-I/O8
OE
D2
RAS
RAS2
CAS2
CAS
DQ16-DQ23
I/O1-I/O8
OE
D3
RAS
CAS3
CAS
DQ24-DQ31
I/O1-I/O8
OE
D4
RAS
A0R - A10R,
A0C - A9C
WE
VCC
C1 - C 4
VSS
D1 - D4
D1 - D4
Block Diagram
Semiconductor Group
4
HYM 322030S/GS-50/-60/-70
2M
×
32-Bit
Absolute Maximum Ratings
Operation temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range......................................................................................... – 55 to 125 °C
Input/output voltage ............................................................................–0.5V to min (Vcc+0.5, 7.0) V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation..................................................................................................................... 4.2 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
CC
= 5 V
±
10 %
Parameter
Symbol
Limit Values
min.
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current
(0 V <
V
IN
< 6.5 V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V <
V
OUT
< 5.5 V)
Average
V
CC
supply current
(RAS, CAS, address cycling,
t
RC
=
t
RC
min)
-50 version
-60 version
-70 version
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
Average
V
CC
supply current
during RAS only refresh cycles
(RAS cycling, CAS =
V
IH
,
t
RC
=
t
RC
min)
-50 version
-60 version
-70 version
max.
Vcc+0.5
0.8
–
0.4
10
10
V
V
V
V
µA
µA
Unit
Test
Condition
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
2.4
– 0.5
2.4
–
– 10
– 10
1)
–
–
–
480
440
400
8
mA
mA
mA
mA
2),3),4)
I
CC2
I
CC3
–
–
–
–
480
440
400
mA
mA
mA
2), 4)
Semiconductor Group
5
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