2M
×
32-Bit Dynamic RAM Module
(Hyper Page Mode - EDO Version)
HYM 322005S/GS-50/-60
•
SIMM modules with 2 097 152 words by 32-bit organization
for PC main memory application
Fast access and cycle time
50 ns access time
84 ns cycle time (-50 version)
60 ns access time
104 ns cycle time (-60 version)
Hyper page mode - EDO capability with
20 ns cycle time (-50 version)
25 ns cycle time (-60 version)
Single + 5 V (± 10 %) supply
Low power dissipation
max. 2200 mW active (-50 version)
max. 1980 mW active (-60 version)
CMOS – 22 mW standby
TTL
– 44 mW standby
CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh
4 decoupling capacitors mounted on substrate
All inputs, outputs and clock fully TTL compatible
72 pin Single in-Line Memory Module
Utilizes four 1M
×
16 -DRAMs in SOJ-42 packages
1024 refresh cycles / 16 ms
Optimized for use in byte-write non-parity applications
Tin-Lead contact pad HYM 322005S
Gold-Lead contact pad HYM 322005GS
single sided module with 20.32 mm (800 mil) height
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Semiconductor Group
1
9.96
HYM 322005S/GS-50/-60
2M
×
32-Bit EDO-Module
The HYM 322005S/GS-50/-60 is a 8 MByte EDO - DRAM module organized as 2 097 152 words by
32-bit in a 72-pin single-in-line package comprising four HYB 5118160BSJ 1M
×
16 EDO - DRAMs
in 400 mil wide SOJ-packages mounted together with four 0.2
µF
ceramic decoupling capacitors on
a PC board.
Each HYB 5118165BSJ is described in the data sheet and is fully electrically tested and processed
according to Siemens standard quality procedure prior to module assembly. After assembly onto
the board, a further set of electrical tests is performed.
The speed of the module can be detected by the use presence detect pins.
The common I/O feature on the HYM 322005S/GS-50/-60 dictates the use of early write cycles.
Ordering Information
Type
HYM 322005S-50
HYM 322005S-60
HYM 322005GS-50
HYM 322005GS-60
Ordering Code
Q67100-Q2066
Q67100-Q2067
Q67100-Q2068
Q67100-Q2069
Package
L-SIM-72-10
L-SIM-72-10
L-SIM-72-10
L-SIM-72-10
Descriptions
EDO - DRAM module
(access time 50 ns)
EDO - DRAM module
(access time 60 ns)
EDO - DRAM module
(access time 50 ns)
EDO - DRAM module
(access time 60 ns)
Semiconductor Group
2
HYM 322005S/GS-50/-60
2M
×
32-Bit EDO-Module
Pin Names
VSS
DQ16
DQ17
DQ18
DQ19
N.C.
A1
A3
A5
N.C.
DQ20
DQ21
DQ22
DQ23
N.C.
A8
RAS3
N.C.
1 DQ0
2
3 DQ1
4
5 DQ2
6
7 DQ3
8
9 VCC 10
11 A0
12
13 A2
14
15 A4
16
17 A6
18
19 DQ4 20
21 DQ5 22
23 DQ6 24
25 DQ7 26
27 A7
28
29 VCC 30
31 A9
32
33 RAS2 34
35 N.C. 36
A0-A9
DQ0-DQ31
CAS0 - CAS3
RAS0 - RAS3
WE
Address Inputs
Data Input/Output
Column Address Strobe
Row Address Strobe
Read/Write Input
Power (+ 5 V)
Ground
Presence Detect Pin
No Connection
V
CC
V
SS
PD
N.C.
N.C.
VSS
CAS2
CAS1
RAS1
WE
DQ8
DQ9
DQ10
DQ11
DQ12
VCC
DQ13
DQ14
DQ15
PD0
PD2
N.C.
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
N.C. 38
CAS0 40
CAS3 42
RAS0 44
N.C. 46
N.C. 48
DQ24 50
DQ25 52
DQ26 54
DQ27 56
DQ28 58
DQ29 60
DQ30 62
DQ31 64
N.C. 66
PD1 68
PD3 70
VSS 72
Presence Detect Pins
-50
PD0
PD1
PD2
PD3
N.C.
N.C.
-60
N.C.
N.C
N.C.
N.C.
V
SS
V
SS
Pin Configuration
Semiconductor Group
3
HYM 322005S/GS-50/-60
2M
×
32-Bit EDO-Module
RAS0
CAS0
CAS1
RAS1
UCAS LCAS RAS
DQ0-DQ7
DQ8-DQ15
I/O1-I/O8
UCAS LCAS RAS
I/O1-I/O8
I/O9-I/O16
OE
I/O9-I/O16
OE
D1
D3
RAS2
CAS2
CAS3
RAS3
UCAS LCAS RAS
DQ16-DQ23
DQ24-DQ31
I/O1-I/O8
UCAS LCAS RAS
I/O1-I/O8
I/O9-I/O16
OE
I/O9-I/O16
OE
D2
D4
A0 - A9
WE
VCC
VSS
C1 -C4
D1 - D4
D1 - D4
Block Diagram
Semiconductor Group
4
HYM 322005S/GS-50/-60
2M
×
32-Bit EDO-Module
Absolute Maximum Ratings
Operating temperature range ......................................................................................... 0 to + 70 °C
Storage temperature range...................................................................................... – 55 to + 125 °C
Input/output voltage ........................................................................................................ – 1 to + 7 V
Power supply voltage...................................................................................................... – 1 to + 7 V
Power dissipation................................................................................................................... 2.52 W
Data out current (short circuit) ................................................................................................ 50 mA
Note:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
DC Characteristics
T
A
= 0 to 70 °C,
V
SS
= 0 V,
V
CC
= 5 V
±
10 %;
t
T
= 2 ns
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 5 mA)
Output low voltage (
I
OUT
= 4.2 mA)
Input leakage current
(0 V
≤
V
IH
≤
Vcc + 0.3V, all other pins = 0 V)
Output leakage current
(DO is disabled, 0 V
≤
V
OUT
≤
Vcc + 0.3V)
Average
V
CC
supply current:
-50 ns version
-60 ns version
(RAS, CAS, address cycling:
t
RC
=
t
RC
min.)
Standby
V
CC
supply current
(RAS = CAS =
V
IH
)
Average
V
CC
supply current, during RAS-only
refresh cycles:
-50 ns version
-60 ns version
(RAS cycling, CAS =
V
I,H,
t
RC
=
t
RC
min.)
Symbol
Limit Values
min.
max.
Vcc+0.5
0.8
–
0.4
10
10
2.4
– 0.5
2.4
–
– 10
– 10
Unit Test
Condition
V
V
V
V
µA
µA
1)
1)
1)
1)
1)
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
I
CC1
1)
–
–
400
360
8
mA
mA
mA
2) 3) 4)
2) 3) 4)
I
CC2
I
CC3
–
–
–
–
400
360
mA
mA
2) 4)
2) 4)
Average
V
CC
supply current,during hyper page
I
CC4
mode (EDO):
-50 ns version
-60 ns version
(RAS =
V
IL
, CAS, address cycling:
(
t
HPC
=
t
HPC
min.)
–
–
180
150
mA
mA
2) 3) 4)
2) 3) 4)
Semiconductor Group
5
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