ADVANCE INFORMATION
DS3650-1·2
SP8720
300MHz43/4
4
The SP8720 is an ECL two-modulus divider, with ECL10K
compatible outputs. It divides by 3 when either of the ECL control
inputs, PE1 or PE2, is in the high state and by 4 when both are low
(or open circuit). An AC coupled input of 600mVp-p is required.
CLOCK INPUT
CONTROL
PE1
INPUTS
PE2
NC
V
CC
NC
NC
OUTPUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
INTERNAL BIAS DECOUPLING
NC
NC
NC
V
EE
DO NOT CONNECT
NC
OUTPUT
FEATURES
s
ECL Compatible Outputs
s
AC-Coupled Input (Internal Bias)
s
Control Inputs ECL III/10K Compatible
QUICK REFERENCE DATA
s
Supply Voltage:
25·2V
SP8720
9
s
Power Consumption: 240mW
s
Temperature Range:
255°C
to
1125°C
(A Grade)
230°C
to
170°C
(B Grade)
DG16
Fig. 1 Pin connections - top view
ABSOLUTE MAXIMUM RATINGS
Supply voltage
Output current
Storage temperature range
Max. junction temperature
Max. clock input voltage
28V
20mA
265°C
to
1150°C
1175°C
2·5V p-p
ORDERING INFORMATION
SP8720 A DG
SP8720 B DG
5962-90577 (SMD)
V
CC
(0V)
5
PE1
PE2
2
3
D1
Q1
D2
Q2
Q2
8
OUTPUT
9
CK
CLOCK INPUT
1
CK
OUTPUT
16
INTERNAL BIAS
DECOUPLING
12
V
EE
Fig. 2 Functional diagram
SP8720
ELECTRICAL CHARACTERISTICS
Unless otherwise stated, the Electrical Characteristics are guaranteed over specified supply, frequency and temperature range
Supply voltage, V
CC
= 0V, V
EE
=
25·2V 6
0·25V
Temperature, T
AMB
=
255°C
to
1125°C
(A Grade),
230°C
to
170°C
(B Grade)
Value
Characteristic
Symbol
f
MAX
f
MIN
I
EE
V
OH
V
OL
V
INH
V
INL
t
p
t
s
t
r
Units
Min.
300
40
65
20·7
21·5
21·62
6
2·5
3
Max.
MHz
MHz
mA
V
V
V
V
ns
ns
ns
Input = 400-800mV p-p
Input = 400-800mV p-p
V
EE
=
25·2V
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
V
EE
=
25·2V
(25°C)
5
5
5
Conditions
Notes
Maximum frequency (sinewave input)
Minimum frequency (sinewave input)
Power supply current
Output high voltage
Output low voltage
PE input high voltage
PE input low voltage
Clock to output delay
Set-up time
Release time
20·85
21·8
20·93
6
3, 6
4, 6
NOTES
1. The temperature coefficients of V
OH
=
11·63mV/°C,
V
OL
=
10·94mV/°C
and of V
IN
=
11·22mV/°C.
2. The test configuration for dynamic testing is shown in Fig.6.
3. The set-up time t
s
is defined as the minimum time that can elapse between L→H transition of control input and the next L→H clock pulse transition
to ensure that the
43
mode is obtained.
4. The release time t
r
is defined as the minimum time that can elapse between H→L transition of control input and the next L→H clock pulse transition
to ensure that the
44
mode is obtained.
5. SP8720B tested at 25°C only.
6. Guaranteed but not tested.
CLOCK INPUT
TRUTH TABLE FOR
CONTROL INPUTS
t
r
t
s
PE1
L
H
L
H
PE2
L
L
H
H
Division ratio
4
3
3
3
PE INPUT
2
OUTPUT
2
1
2
Fig. 3 Timing diagram
2000
INPUT AMPLITUDE (mV p-p)
1600
T
AMB
=
255°C
TO
1125°C
1200
800
GUARANTEED
*
OPERATING
WINDOW
*
Tested as specified
in table of Electrical
Characteristics
400
0
0
100
200
INPUT FREQUENCY (MHz)
300
400
Fig. 4 Typical input characteristic of SP8720A
2
SP8720
OPERATING NOTES
1. The clock input is biased internally and is coupled to the signal
source with a suitable capacitor. The input signal path is completed
by an input reference decoupling capacitor which is connected
from pin 16 to ground.
2. If no signal is present the device will self-oscillate. If this is
undesirable, it may be prevented by connecting a 15kΩ resistor
from the clock input (pin 1) to V
EE
. This will reduce the input
sensitivity by approximately 100mV.
3. The circuit will operate down to DC but slew rate must be better
than 100V/µs.
4. The Q and Q outputs are compatible with ECLII but can be
interfaced to ECL10K as shown in Fig. 7. There is an internal
circuit equivalent to a load of 2kΩ at each output.
5. The PE inputs are ECLIII/10K compatible and include 4·3kΩ
pulldown resistors. Unused inputs can therefore be left open.
6. The input impedance of the SP8720 varies as a function of
frequency, see Fig. 5.
7. All components should be suitable for the frequency in use.
j1
j
0.5
j2
j
0.2
j5
0
0.2
0.5
1
2
5
50
300
100
2
j
0.2
250
200
150
2
j
5
2
j
0.5
2
j
1
2
j
2
Fig. 5 Typical input impedance. Test conditions: Supply Voltage =
2
5·2V,
Ambient Temperature = 25°C. Frequencies in MHz, impedances normalised to 50Ω.
1n
INPUT FROM
GENERATOR
33
TO SAMPLING
SCOPE
33
1
16
1n
20
5
8
450
450
100n
100n
OUTPUTS TO
SAMPLING
SCOPE
DUT
12
9
V
EE
=
25·2V
1n
Fig. 6 Test circuit
3
SP8720
ECL CONTROL INPUTS
0=4
1=3
PE1
1n
CLOCK
INPUT
5
1
4·3k
400
2
PE2
3
4·3k
8
DIVIDE BY
3/4
BIAS
9
47
ECL10K
OUTPUT
1·5k
12
V
EE
1n
16
1n
15k
2k
2k
Fig. 7 Typical application circuit showing interfacing
4
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