Femtoclock™ Crystal-to-HSTL Clock
Generator
842023
DATA SHEET
General Description
The 842023 is an Ethernet Clock Generator. For Ethernet
applications, a 25MHz crystal is used to generate 250MHz. The
842023 uses IDT 3
rd
generation low phase noise VCO technology
and can achieve <1ps rms phase jitter, easily meeting Ethernet jitter
requirements. The 842023 is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
Features
•
•
•
•
•
•
•
•
One differential HSTL output pair
Crystal oscillator interface, 18pF parallel resonant crystal
(24.5MHz – 34MHz)
Output frequency range: 245MHz – 340MHz
VCO range: 490MHz – 680MHz
RMS phase jitter at: 250MHz, using a 25MHz crystal (1.875MHz –
20MHz): 0.36ps (typical)
Full 3.3V or 2.5V output supply modes
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
Frequency Table
Inputs
Crystal Frequency (MHz)
25
M
20
N
2
Multiplication Value M/N
10
Output Frequency (MHz)
250
Block Diagram
OE
Pullup
Pin Assignment
V
DDA
GND
XTAL_OUT
XTAL_IN
1
2
3
4
8
7
6
5
V
DD
Q
nQ
OE
XTAL_IN
OSC
XTAL_OUT
Phase
Detector
VCO
490MHz - 680MHz
N = ÷2
(fixed)
Q
nQ
M = ÷20
(fixed)
842023
8 Lead TSSOP
4.40mm x 3.0mm x 0.925 package body
G Package
Top View
842023 Rev A 8/14/15
1
©2015 Integrated Device Technology, Inc.
842023 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
3,
4
5
6, 7
8
Name
V
DDA
GND
XTAL_OUT,
XTAL_IN
OE
nQ, Q
V
DD
Power
Power
Input
Input
Output
Power
Pullup
Type
Description
Analog supply pin.
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Output enable pin. When HIGH, Q/nQ outputs are active. When LOW, the
Q/nQ outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Differential output pair. HSTL interface levels.
Core supply pin.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
50mA
100mA
129.5C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Power Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.11
Typical
3.3
3.3
Maximum
3.465
V
DD
84
11
Units
V
V
mA
mA
FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR
2
Rev A 8/14/15
842023 DATA SHEET
Table 3B. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
DD
V
DDA
I
DD
I
DDA
Parameter
Power Supply Voltage
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.11
Typical
2.5
2.5
Maximum
2.625
V
DD
80
11
Units
V
V
mA
mA
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5% or 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input High Current
Input Low Current
OE
OE
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
-150
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
5
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 3D. HSTL DC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Output Crossover
Voltage; NOTE 2
Peak-to-Peak
Output Voltage Swing
Test Conditions
Minimum
1.0
0
40% x (V
OH
- V
OL
) + V
OL
0.4
Typical
Maximum
1.8
0.6
60% x (V
OH
- V
OL
) + V
OL
1.8
Units
V
V
V
V
NOTE 1: Outputs terminated with 50 to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Table 3E. HSTL DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Symbol
V
OH
V
OL
V
OX
V
SWING
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Output Crossover
Voltage; NOTE 2
Peak-to-Peak Output
Voltage Swing
40% x (V
OH
- V
OL
) + V
OL
0.4
Test Conditions
Minimum
0.9
Typical
Maximum
1.4
0.4
60% x (V
OH
- V
OL
) + V
OL
1.4
Units
V
V
V
V
NOTE 1: Outputs terminated with 50 to GND.
NOTE 2: Defined with respect to output voltage swing at a given condition.
Rev A 8/14/15
3
FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR
842023 DATA SHEET
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: It is not recommended to overdrive the crystal input with an external clock.
24.5
Test Conditions
Minimum
Typical
Fundamental
34
50
7
MHz
Maximum
Units
pF
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= 3.3V ± 5%, T
A
= 0°C to 70°C
Parameter
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Symbol
Output Frequency
RMS Phase Jitter,
Random; NOTE 1
Output Rise/Fall Time
Output Duty Cycle
250MHz
Integration Range: 1.875MHz – 20MHz
20% to 80%
200
48
Test Conditions
Minimum
245
0.36
700
52
Typical
Maximum
340
Units
MHz
ps
ps
%
NOTE 1: Please refer to Phase Noise Plots.
Table 5B. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= 0°C to 70°C
Parameter
f
OUT
tjit(Ø)
t
R
/ t
F
odc
Symbol
Output Frequency
RMS Phase Jitter,
Random; NOTE 1
Output Rise/Fall Time
Output Duty Cycle
250MHz
Integration Range: 1.875MHz – 20MHz
20% to 80%
200
48
Test Conditions
Minimum
245
0.32
700
52
Typical
Maximum
340
Units
MHz
ps
ps
%
NOTE 1: Please refer to Phase Noise Plots.
FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR
4
Rev A 8/14/15
842023 DATA SHEET
Typical Phase Noise at 250MHz (3.3V)
250MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.36ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
Rev A 8/14/15
5
FEMTOCLOCK™ CRYSTAL-TO-HSTL CLOCK GENERATOR
FPGA/CPLD
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