Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
6 TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
)
..........42°C/W
Junction-to-Case Thermal Resistance (θ
JC
)
.................9°C/W
Package Thermal Characteristics
(Note 1)
8 TDFN
Junction-to-Ambient Thermal Resistance (θ
JA
)
..........41°C/W
Junction-to-Case Thermal Resistance (θ
JC
)
.................8°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
CC
= 1.2V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25°C.) (Note 2)
PARAMETER
Supply Voltage
SYMBOL
V
CC
CONDITIONS
T
A
= 0°C to +125°C
T
A
= -40°C to 0°C
V
CC
= 5.0V, T
A
=
-40°C to +85°C
V
CC
= 3.3V, T
A
=
-40°C to +85°C
V
CC
> V
TH
+ 150mV,
no load, reset output
deasserted (Note 3)
V
CC
= 1.8V, T
A
=
-40°C to +85°C
V
CC
= 5.0V, T
A
=
-40°C to +125°C
V
CC
= 3.3V, T
A
=
-40°C to +125°C
V
CC
= 1.8V, T
A
=
-40°C to +125°C
V
CC
< V
TH
, no load, reset output asserted
V
CC
Reset Threshold
Hysteresis
V
TH
V
HYST
V
CC
falling (see Table 1)
V
CC
rising
T
A
= +25°C
T
A
= -40°C to
+125°C
V
TH
-
1.5%
V
TH
-
2.5%
0.5
MIN
1.1
1.2
142
132
125
142
132
125
7
TYP
MAX
5.5
5.5
210
185
175
nA
430
415
400
15
V
TH
+
1.5%
V
TH
+
2.5%
µA
UNITS
V
Supply Current
I
CC
V
%
www.maximintegrated.com
Maxim Integrated │
2
MAX16056–MAX16059
125nA nanoPower Supervisory Circuits
with Capacitor-Adjustable Reset
and Watchdog Timeouts
Electrical Characteristics (continued)
(V
CC
= 1.2V to 5.5V, T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at V
CC
= 3.3V, T
A
= +25°C.) (Note 2)
PARAMETER
V
CC
to Reset Delay
Reset Timeout Period
SRT Ramp Curren
t
SRT Ramp Threshold
Watchdog Timeout Clock Period
SYMBOL
t
RD
t
RP
I
RAMP1
V
RAMP1
t
WDPER
CONDITIONS
V
CC
falling from (V
TH
+ 100mV) to
(V
TH
- 100mV) at 10mV/µs
C
SRT
= 2700pF (Note 4)
V
SRT
= 0V to V
RAMP1
,
V
CC
= 1.6V to 5V
T
A
= -40°C to
+125°C
T
A
= +25°C
10.5
197
210
1.173
5
3.5
T
A
= -40°C to
+125°C
T
A
= +25°C
197
210
1.173
MIN
TYP
80
14.18
240
240
1.235
6.4
6.4
240
240
1.235
17.0
282
nA
270
1.297
8
9.5
282
270
1.297
0.3
0.3
0.4
0.8 x
V
CC
0.8 x
V
CC
0.8 x
V
CC
1.0
0.7 x
V
CC
0.3 x
V
CC
1
200
t
MRD
(Note 5)
MR,
WDI, WDS is connected to GND or V
CC
150
-100
+100
250
µA
V
V
ms
MAX
UNITS
µs
ms
V
CC
= 1.6V to 5V (V
RAMP
rising)
T
A
= +25°C
T
A
= -40°C to +125°C
V
SWT
= 0V to V
RAMP2
,
V
CC
= 1.6V to 5V
SWT Ramp Current
SWT Ramp Threshold
I
RAMP2
V
RAMP2
V
OL
nA
V
V
CC
= 1.6V to 5V (V
RAMP2
rising)
V
CC
≥ 1.0V, I
SINK
= 50µA
V
CC
≥ 2.7V, I
SINK
= 1.2mA
V
CC
≥ 4.5V, I
SINK
= 3.2mA
V
CC
≥ 1.8V,
I
SOURCE
= 200µA
RESET
Output Voltage
V
OH
MAX16056/MAX16057
V
CC
≥ 2.25V,
I
SOURCE
= 500µA
V
CC
≥ 4.5V,
I
SOURCE
= 800µA
RESET
Output-Leakage Current,
Open Drain
I
LKG
V
IH
V
IL
V
CC
> V
TH
, reset not asserted, V
RESET
=
5.5V (MAX16058/MAX16059)
Input-Logic Levels
V
MR
Minimum Pulse Width
MR
Glitch Rejection
MR-to-RESET
Delay
WDI Minimum Pulse Width
Input Leakage Current
Note
Note
Note
Note
2:
3:
4:
5:
t
MPW
µs
ns
ns
ns
nA
Devices are production tested at T
A
= +25°C. Specifications over temperature limits are guaranteed by design.
WDI input period is 1s with t
RISE
and t
FALL
< 50ns.
Worst case of SRT ramp current and voltage is used to guarantee minimum and maximum limits.
stm32/stm8
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