DUAL CHANNEL E1
SHORT HAUL LINE INTERFACE UNIT
FEATURES:
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Dual channel E1 short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
- ANSI T1.102
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
Software programmable or hardware selectable on:
- Wave-shaping templates
- Line terminating impedance (E1: 75
Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
- HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
- High impedance setting for line drivers
IDT82V2052E
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•
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•
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•
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- PRBS (Pseudo Random Bit Sequence) generation and detection
with 2
15
-1 PRBS polynomials
- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS error
counter
- Analog loopback, Digital loopback, Remote loopback
Adaptive receive sensitivity up to -20 dB (Host Mode only)
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection and internal protection diode for line
drivers
LOS (Loss Of Signal) detection with programmable LOS levels
(Host Mode only)
AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces and hardware control mode
Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2042E T1/E1/J1 Short Haul LIU
Available in 80-pin TQFP
Green package options available
DESCRIPTION:
The IDT82V2052E is a dual channel E1 Line Interface Unit. The
IDT82V2052E performs clock/data recovery, AMI/HDB3 line decoding and
detects and reports the LOS conditions. An integrated Adaptive Equalizer
is available to increase the receive sensitivity and enable programming of
LOS levels. In transmit path, there is an AMI/HDB3 encoder and Waveform
Shaper. There is one Jitter Attenuator, which can be placed in either the
receive path or the transmit path. The Jitter Attenuator can also be disabled.
The IDT82V2052E supports both Single Rail and Dual Rail system inter-
faces. To facilitate the network maintenance, a PRBS generation/detection
circuit is integrated in the chip, and different types of loopbacks can be set
according to the applications. Two different kinds of line terminating imped-
ance, 75
Ω
and 120
Ω
are selectable on a per channel basis. The chip also
provides driver short-circuit protection and internal protection diode and
supports JTAG boundary scanning. The chip can be controlled by either
software or hardware.
The IDT82V2052E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
1
2005 Integrated Device Technology, Inc.
December 12, 2005
DSC-6779/1
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
LOSn
LOS/AIS
Detector
Data and
Clock
Recovery
Adaptive
Equalizer
One of the Two Identical Channels
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Decoder
PRBS Detector
Jitter
Attenuator
Data
Slicer
Receiver
Internal
Termination
Analog
Loopback
RTIPn
RRINGn
Remote
Loopback
Digital
Loopback
Waveform
Shaper
Line
Driver
Transmitter
Internal
Termination
TCLKn
TDn/TDPn
TDNn
HDB3/AMI
Decoder
PRBS Generator
TAOS
Jitter
Attenuator
TTIPn
TRINGn
Clock
Generator
Software Control Interface
Register
Files
Pin Control
JTAG TAP
G.772
Monitor
TRST
TCK
TMS
INT
CS
SDO
SCLK
R/W/WR/SDI
RD/DS/SCLKE
A[5:0]
D[7:0]
MODE[1:0]
TERMn
RXTXM[1:0]
PULSn
PATTn[1:0]
JA[1:0]
MONTn
LPn[1:0]
THZ
RCLKE
RPDn
RST
TDI
TDO
VDDIO
VDDD
VDDA
VDDT
VDDR
MCLK
Figure-1 Block Diagram
FUNCTIONAL BLOCK DIAGRAM
2
December 12, 2005
Table of Contents
1
2
3
IDT82V2052E PIN CONFIGURATIONS ....................................................................................... 8
PIN DESCRIPTION ....................................................................................................................... 9
FUNCTIONAL DESCRIPTION .................................................................................................... 17
3.1
CONTROL MODE SELECTION ....................................................................................... 17
3.2
TRANSMIT PATH ............................................................................................................. 17
3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17
3.2.2 ENCODER .............................................................................................................. 17
3.2.3 PULSE SHAPER .................................................................................................... 17
3.2.3.1 Preset Pulse Templates .......................................................................... 17
3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 18
3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 20
3.2.5 TRANSMIT PATH POWER DOWN ........................................................................ 20
3.3
RECEIVE PATH ............................................................................................................... 20
3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 20
3.3.2 LINE MONITOR ...................................................................................................... 21
3.3.3 ADAPTIVE EQUALIZER......................................................................................... 22
3.3.4 RECEIVE SENSITIVITY ......................................................................................... 22
3.3.5 DATA SLICER ........................................................................................................ 22
3.3.6 CDR (Clock & Data Recovery)................................................................................ 22
3.3.7 DECODER .............................................................................................................. 22
3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 22
3.3.9 RECEIVE PATH POWER DOWN........................................................................... 23
3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 23
3.4
JITTER ATTENUATOR .................................................................................................... 24
3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 24
3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 24
3.5
LOS AND AIS DETECTION ............................................................................................. 25
3.5.1 LOS DETECTION ................................................................................................... 25
3.5.2 AIS DETECTION .................................................................................................... 26
3.6
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 27
3.6.1 TRANSMIT ALL ONES ........................................................................................... 27
3.6.2 TRANSMIT ALL ZEROS......................................................................................... 27
3.6.3 PRBS GENERATION AND DETECTION ............................................................... 27
3.7
LOOPBACK ...................................................................................................................... 27
3.7.1 ANALOG LOOPBACK ............................................................................................ 27
3.7.2 DIGITAL LOOPBACK ............................................................................................. 27
3.7.3 REMOTE LOOPBACK............................................................................................ 27
Table of Contents
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December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
4
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 30
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 30
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 30
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 31
LINE DRIVER FAILURE MONITORING ........................................................................... 31
MCLK AND TCLK ............................................................................................................. 32
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 32
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 32
MICROCONTROLLER INTERFACES ............................................................................. 33
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 33
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 33
INTERRUPT HANDLING .................................................................................................. 34
5V TOLERANT I/O PINS .................................................................................................. 35
RESET OPERATION ........................................................................................................ 35
POWER SUPPLY ............................................................................................................. 35
PROGRAMMING INFORMATION .............................................................................................. 36
4.1
REGISTER LIST AND MAP ............................................................................................. 36
4.2
Reserved Registers .......................................................................................................... 36
4.3
REGISTER DESCRIPTION .............................................................................................. 38
4.3.1 GLOBAL REGISTERS............................................................................................ 38
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER ....................................... 39
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 39
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 40
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 42
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 43
4.3.7 INTERRUPT CONTROL REGISTERS ................................................................... 45
4.3.8 LINE STATUS REGISTERS ................................................................................... 47
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 48
4.3.10 COUNTER REGISTERS ........................................................................................ 49
HARDWARE CONTROL PIN SUMMARY .................................................................................. 50
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52
6.1
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53
6.2
JTAG DATA REGISTER ................................................................................................... 53
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR) ........................................................ 53
6.2.2 BYPASS REGISTER (BR)...................................................................................... 53
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53
6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 53
TEST SPECIFICATIONS ............................................................................................................ 56
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 65
8.1
SERIAL INTERFACE TIMING .......................................................................................... 65
8.2
PARALLEL INTERFACE TIMING ..................................................................................... 66
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December 12, 2005
5
6
7
8
Table of Contents
List of Tables
Table-1
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
List of Tables
Pin Description ................................................................................................................ 9
Transmit Waveform Value For E1 75 Ohm ................................................................... 19
Transmit Waveform Value For E1 120 Ohm ................................................................. 19
Impedance Matching for Transmitter ............................................................................ 20
Impedance Matching for Receiver ................................................................................ 21
Criteria of Starting Speed Adjustment........................................................................... 24
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 25
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 26
AIS Condition ................................................................................................................ 26
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 27
EXZ Definition ............................................................................................................... 30
Interrupt Event............................................................................................................... 34
Global Register List and Map........................................................................................ 36
Per Channel Register List and Map .............................................................................. 37
ID: Device Revision Register ........................................................................................ 38
RST: Reset Register ..................................................................................................... 38
GCF: Global Configuration Register ............................................................................. 38
INTCH: Interrupt Channel Indication Register............................................................... 38
TERM: Transmit and Receive Termination Configuration Register .............................. 39
JACF: Jitter Attenuation Configuration Register ........................................................... 39
TCF0: Transmitter Configuration Register 0 ................................................................. 40
TCF1: Transmitter Configuration Register 1 ................................................................. 40
TCF2: Transmitter Configuration Register 2 ................................................................. 41
TCF3: Transmitter Configuration Register 3 ................................................................. 41
TCF4: Transmitter Configuration Register 4 ................................................................. 41
RCF0: Receiver Configuration Register 0..................................................................... 42
RCF1: Receiver Configuration Register 1..................................................................... 42
RCF2: Receiver Configuration Register 2..................................................................... 43
MAINT0: Maintenance Function Control Register 0...................................................... 43
MAINT1: Maintenance Function Control Register 1...................................................... 44
MAINT6: Maintenance Function Control Register 6...................................................... 44
INTM0: Interrupt Mask Register 0 ................................................................................. 45
INTM1: Interrupt Masked Register 1 ............................................................................. 45
INTES: Interrupt Trigger Edge Select Register ............................................................. 46
STAT0: Line Status Register 0 (real time status monitor)............................................. 47
STAT1: Line Status Register 1 (real time status monitor)............................................. 48
INTS0: Interrupt Status Register 0 ................................................................................ 48
INTS1: Interrupt Status Register 1 ................................................................................ 49
CNT0: Error Counter L-byte Register 0......................................................................... 49
CNT1: Error Counter H-byte Register 1 ........................................................................ 49
Hardware Control Pin Summary ................................................................................... 50
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December 12, 2005
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