Si826x
5
K
V LED E
MULATOR
I
NPUT
, 4.0 A I
SOLATED
G
ATE
D
RIVERS
Features
Pin-compatible, drop-in upgrades for
popular high speed opto-coupled
gate drivers
Low power diode emulator simplifies
design-in process
0.6 and 4.0 Amp peak output drive
current
Rail-to-rail output voltage
Performance and reliability
advantages vs. opto-drivers
Resistant to temperature and age
10x lower FIT rate for longer
service life
14x tighter part-to-part matching
Higher common-mode transient
immunity: >50 kV/µs typical
Robust protection features
Multiple UVLO ordering options
(5, 8, and 12 V) with hysteresis
60 ns propagation delay,
independent of input drive current
Wide V
DD
range: 6.5 to 30 V
Up to 5000 V
RMS
isolation
10 kV surge withstand capability
AEC-Q100 qualified
Wide operating temperature range
–40 to +125 °C
RoHS-compliant packages
SOIC-8 (Narrow body)
DIP8 (Gull-wing)
SDIP6 (Stretched SO-6)
LGA8
Pin Assignments:
See page 22
1
UVLO
8
VDD
ANODE
2
e
7
VO
CATHODE
3
6
VO
NC
4
5
GND
SOIC-8, DIP8, LGA8
Industry Standard Pinout
ANODE 1
6
UVLO
VDD
Applications
IGBT/ MOSFET gate drives
Industrial, HEV and renewable
energy inverters
AC, Brushless, and DC motor
controls and drives
Variable speed motor control in
consumer white goods
Isolated switch mode and UPS
power supplies
NC 2
e
5
VO
CATHODE 3
4
GND
SDIP6
Industry Standard Pinout
Safety Regulatory Approvals
UL 1577 recognized
VDE certification conformity
Up to 5000 Vrms for 1 minute
IEC60747-5-2/VDE0884-10
(basic/reinforced insulation)
CSA component notice 5A approval
CQC certification approval
IEC 60950-1, 61010-1, 60601-1
GB4943.1
(reinforced insulation)
Patent pending
Description
The Si826x isolators are pin-compatible, drop-in upgrades for popular opto-
coupled gate drivers, such as 0.6 A ACPL-0302/3020, 2.5 A HCPL-3120/ACPL-
3130, HCNW3120/3130, and similar opto-drivers. The devices are ideal for driving
power MOSFETs and IGBTs used in a wide variety of inverter and motor control
applications. The Si826x isolated gate drivers utilize Silicon Laboratories'
proprietary silicon isolation technology, supporting up to 5.0 kV
RMS
withstand
voltage per UL1577 and 10kV surge protection per IEC60747. This technology
enables higher-performance, reduced variation with temperature and age, tighter
part-to-part matching, and superior common-mode rejection compared to opto-
coupled gate drivers. While the input circuit mimics the characteristics of an LED,
less drive current is required, resulting in higher efficiency. Propagation delay time
is independent of input drive current, resulting in consistently short propagation
times, tighter unit-to-unit variation, and greater input circuit design flexibility. As a
result, the Si826x series offers longer service life and dramatically higher reliability
compared to opto-coupled gate drivers.
Rev. 1.3 5/15
Copyright © 2015 by Silicon Laboratories
Si826x
Si826x
Functional Block Diagram
Diode
Emulator
VDD
A1
REC
XMIT
I
F
Output Driver
OUT
C1
GND
2
Rev. 1.3
Si826x
T
ABLE
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4. Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.1. Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.2. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4.3. Under Voltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.1. Input Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2. Output Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3. Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.4. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
6. Pin Descriptions (SOIC-8, DIP8, LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
7. Pin Descriptions (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
11. Package Outline: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
12. Land Pattern: DIP8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
13. Package Outline: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
14. Land Pattern: SDIP6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
15. Package Outline: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
16. Land Pattern: LGA8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.1. Si826x Top Marking (Narrow Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
17.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
17.3. Si826x Top Marking (DIP8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.4. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
17.5. Si826x Top Marking (SDIP6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.6. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
17.7. Si826x Top Marking (LGA8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
17.8. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Rev. 1.3
3
Si826x
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Supply Voltage
Input Current
Operating Temperature (Ambient)
Symbol
V
DD
I
F(ON)
(see Figure 1)
T
A
Min
6.5
6
–40
Typ
—
—
—
Max
30
30
125
Unit
V
mA
°C
Table 2. Electrical Characteristics
1
V
DD
= 15 V or 30 V, GND = 0 V, I
F
= 6 mA, T
A
= –40 to +125 °C; typical specs at 25 °C
Parameter
DC Parameters
Supply Voltage
2
Supply Current (Output High)
Symbol
Test Condition
Min
Typ
Max
Unit
V
DD
I
DD
(V
DD
– GND)
I
F
= 10 mA
V
DD
= 15 V
V
DD
= 30 V
V
F
= 0 V; I
F
= 0 mA
V
DD
= 15 V
V
DD
= 30 V
6.5
—
—
—
—
—
—
—
1.8
2.0
1.5
1.7
—
0.34
—
—
30
2.4
2.7
2.1
2.4
3.6
—
1
2.8
V
mA
mA
mA
mA
mA
mA
V
V
Supply Current (Output Low)
Input Current Threshold
Input Current Hysteresis
Input Forward Voltage (OFF)
Input Forward Voltage (ON)
Input Capacitance
I
DD
I
F(TH)
I
HYS
V
F(OFF)
V
F(ON)
C
I
Measured at ANODE with
respect to CATHODE.
Measured at ANODE with
respect to CATHODE.
f = 100 kHz,
V
F
= 0 V,
V
F
= 2 V
Si826xAxx devices
Si826xBxx devices (I
OH
= -1 A)
Si826xAxx devices
Si826xBxx devices (I
OL
= 2 A)
—
1.6
—
—
—
—
—
—
15
15
15
2.6
5
0.8
—
—
—
5.1
—
2.0
pF
Output Resistance High
(Source)
3
Output Resistance Low (Sink)
3
R
OH
R
OL
Notes:
1.
See "8.Ordering Guide" on page 23 for more information.
2.
Minimum value of (V
DD
- GND) decoupling capacitor is 1
µ
F.
3.
Both V
O
pins are required to be shorted together for 4.0 A compliance.
4.
When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic
inductances, which may cause over-stress conditions due to excessive ringing.
5.
Guaranteed by characterization.
4
Rev. 1.3
Si826x
Table 2. Electrical Characteristics (Continued)
1
V
DD
= 15 V or 30 V, GND = 0 V, I
F
= 6 mA, T
A
= –40 to +125 °C; typical specs at 25 °C
Parameter
Symbol
Test Condition
Si826xAxx devices (I
F
= 0),
(t
PW_IOH
< 250 ns)
(see Figure 3)
Min
—
Typ
0.4
Max
—
Unit
Output High Current (Source)
3,4
I
OH
Si826xBxx devices (I
F
= 0),
(t
PW_IOH
< 250 ns),
(V
DD
– V
O
= 7.5 V)
(see Figure 3)
Si826xAxx devices
(I
F
= 10 mA),
(t
PW_IOL
< 250 ns)
(see Figure 2)
A
0.5
1.8
—
—
0.6
—
A
Output Low Current (Sink)
3,4
I
OL
Si826xBxx devices
(I
F
= 10 mA),
(t
PW_IOL
< 250 ns),
(V
O
- GND = 4.2 V)
(see Figure 2)
Si826xAxx devices
(I
OUT
= –100 mA)
1.2
4.0
—
—
V
DD
–
0.5
—
V
DD
–
0.4
V
DD
–
0.25
V
DD
—
—
High-Level Output Voltage
V
OH
Si826xBxx devices
(I
OUT
= –100 mA)
Si826xBxx devices
(I
OUT
= 0 mA),
(I
F
= 0 mA)
Si826xAxx devices
(I
OUT
= 100 mA),
(I
F
= 10 mA)
Si826xBxx devices
(I
OUT
= 100 mA),
(I
F
= 10 mA)
See Figure 11 on page 16.
V
DD
rising
See Figure 11 on page 16.
V
DD
falling
V
—
—
320
—
mV
Low-Level Output Voltage
V
OL
—
5
4.7
—
80
5.6
5.3
300
200
6.3
6.0
—
V
V
mV
UVLO Threshold +
(Si826xxAx mode)
UVLO Threshold –
(Si826xxAx mode)
UVLO lockout hysteresis
(Si826xxAx mode)
VDD
UV+
VDD
UV–
VDD
HYS
Notes:
1.
See "8.Ordering Guide" on page 23 for more information.
2.
Minimum value of (V
DD
- GND) decoupling capacitor is 1
µ
F.
3.
Both V
O
pins are required to be shorted together for 4.0 A compliance.
4.
When performing this test, it is recommended that the DUT be soldered down to the PCB to reduce parasitic
inductances, which may cause over-stress conditions due to excessive ringing.
5.
Guaranteed by characterization.
Rev. 1.3
5
FPGA/CPLD
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