FemtoClock® SAS/ SATA Clock Generator
Datasheet
844441
General Description
The 844441 is a low jitter, high performance clock generator and a
member of the FemtoClock
®
family of silicon timing products. The
844441 is designed for use in applications using the SAS and SATA
interconnect. The 844441 uses an external, 25MHz, parallel
resonant crystal to generate four selectable output frequencies:
75MHz, 100MHz, 150MHz, and 300MHz. This silicon based
approach provides excellent frequency stability and reliability. The
844441 features down and center spread spectrum (SSC) clocking
techniques.
Features
•
•
•
•
•
•
•
Designed for use in SAS, SAS-2, and SATA systems
Center (±0.17%) Spread Spectrum Clocking (SSC)
Down (-0.23% or -0.5%) SSC
Better frequency stability than SAW oscillators
One differential 2.5V LVDS output
Crystal oscillator interface designed for 25MHz
(C
L
= 12pF) frequency
External fundamental crystal frequency ensures high reliability
and low aging
Selectable output frequencies: 75MHz, 100MHz, 150MHz,
300MHz
Output frequency is tunable with external capacitors
RMS phase jitter @ 100MHz, using a 25MHz crystal
(12kHz – 20MHz): 1.1936ps (typical)
2.5V operating supply
-40°C to 85°C ambient operating temperature
Lead-free (RoHS 6) packaging
Applications
•
•
•
•
•
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SAS/SATA Host Bus Adapters
SATA Port Multipliers
SAS I/O Controllers
TapeDrive and HDD Array Controllers
SAS Edge and Fanout Expanders
HDDs and TapeDrives
Disk Storage Enterprise
•
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Pin Assignment
Block Diagrams
XTAL_IN
XTAL_OUT
XTAL_IN
SSC_SEL0
SSC_SEL1
1
2
3
4
8
7
6
5
GND
nQ
Q
V
DD
25MHz
XTAL
XTAL_OUT
OSC
FemtoClock™
PLL
00 = SSC Off
01 = 0.5% Down-spread
10 = 0.23% Down-spread
11 = 0.5% Center-spread
Q
nQ
844441
8-Lead SOIC, 3.90mm x 4.90mm Package
SSC_SEL(1:0)
Pulldown:Pulldown
SSC Output
Control Logic
8-Lead SOIC
nPLL_SEL
Pulldown
GND
XTAL_IN
25MHz
XTAL
XTAL_OUT
OSC
FemtoClock™
PLL
0
1
00 = 75MHz
01 = 100MHz
10 = 150MHz
(default)
11 = 300MHz
Q
nQ
XTAL_OUT
XTAL_IN
SSC_SEL0
nc
nc
nc
SSC_SEL1
1
2
3
4
5
6
7
8
F_SEL(1:0)
SSC_SEL(1:0)
Pullup:Pulldown
Pulldown:Pulldown
Clock Output
Control Logic
16
15
14
13
12
11
10
9
F_SEL1
GND
nPLL_SEL
nQ
Q
V
DD
F_SEL0
V
DD
16-Lead TSSOP
844441
16-Lead TSSOP, 4.4mm x 5.0mm Package
©2016 Integrated Device Technology, Inc.
1
Revison E, November 2, 2016
844441 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Name
XTAL_OUT,
XTAL_IN
SSC_SEL0,
SSC_SEL1
F_SEL0
F_SEL1
nPLL_SEL
Q, nQ
GND
V
DD
nc
Input
Input
Input
Input
Input
Output
Power
Power
Unused
Pulldown
Pulldown
Pullup
Pulldown
Type
Description
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
SSC select pins. See Table 3A. LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
Output frequency select pin. See Table 3B. LVCMOS/LVTTL interface levels.
PLL Bypass pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. LVDS interface levels.
Power supply ground.
Power supply pin.
No connect.
NOTE:
Pullup/Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
nPLL_SEL, F_SEL[1:0], SSC_SEL[1:0]
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3A. SSC_SEL[1:0] Function Table
Inputs
SSC_SEL1
0 (default)
0
1
1
SSC_SEL0
0 (default)
1
0
1
Mode
SSC Off
0.5% Down-spread
0.23% Down-spread
0.34% Center-spread
F_SEL1
0
0
1 (default)
1
Table 3B. F_SEL[1:0] Function Table
Inputs
F_SEL0
0
1
0 (default)
1
Output Frequency (MHz)
75
100
150
300
©2016 Integrated Device Technology, Inc.
2
Revison E, November 2, 2016
844441 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
16 Lead TSSOP
8 Lead SOIC
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
10mA
15mA
81.2°C/W (0 mps)
96.0°C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
73
Units
V
mA
Table 4B. LVCMOS/LVTTL DC Characteristics,V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
Input
High
Current
Input
Low
Current
F_SEL1
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
F_SEL1
SSC_SEL[0:1],
F_SEL0, nPLL_SEL
V
DD
= V
IN
= 2.5V
V
DD
= V
IN
= 2.5V
V
DD
= 2.5V, V
IN
= 0V
V
DD
= 2.5V, V
IN
= 0V
-150
-5
Test Conditions
Minimum
1.7
-0.3
Typical
Maximum
V
DD
+ 0.3
0.7
5
150
Units
V
V
µA
µA
µA
µA
I
IL
Table 4C. LVDS DC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1
Test Conditions
Minimum
200
Typical
Maximum
454
50
1.375
50
Units
mV
mV
V
mV
©2016 Integrated Device Technology, Inc.
3
Revison E, November 2, 2016
844441 Datasheet
Table 4D. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Load Capacitance (C
L
)
12
Test Conditions
Minimum
Typical
Fundamental
25
50
7
MHz
Ohm
pF
pF
Maximum
Units
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
Parameter
Test Conditions
F_SEL(1:0) = 00
F_SEL(1:0) = 01
f
OUT
Output Frequency
F_SEL(1:0) = 10
F_SEL(1:0) = 11
75MHz, Integration Range:
12kHz – 20MHz
100MHz, Integration Range:
12kHz – 20MHz
150MHz, Integration Range:
12kHz – 20MHz
300MHz, Integration Range:
12kHz – 20MHz
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
45
150
300
1.19602
1.1936
1.22743
1.15011
400
55
MHz
MHz
ps
ps
ps
ps
ps
%
Minimum
Typical
75
100
Maximum
Units
MHz
MHz
tjit(Ø)
RMS Phase Jitter
(Random); NOTE 1
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using a 25MHz, 12pF quartz crystal.
NOTE 1: Please refer to the Phase Noise plot.
©2016 Integrated Device Technology, Inc.
4
Revison E, November 2, 2016
844441 Datasheet
Typical Phase Noise at 100MHz
Noise Power (dBc / Hz)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
5
Revison E, November 2, 2016
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