EVALUATION KIT AVAILABLE
AVAILAB
LE
MAX3420E
USB Peripheral Controller
with SPI Interface
General Description
Features
♦
Microprocessor-Independent USB Solution
♦
Complies with USB Specification Revision 2.0
(Full-Speed Operation)
♦
Integrated Full-Speed USB Transceiver
♦
Firmware/Hardware Control of an Internal D+
Pullup Resistor
♦
Programmable 3- or 4-Wire 26MHz SPI Interface
♦
Level Translators and V
L
Input Allow Independent
System Interface Voltage
♦
Internal Comparator Detects V
BUS
for
Self-Powered Applications
♦
ESD Protection on D+, D-, and VBCOMP
♦
Interrupt Output Pin (Level or Programmable
Edge) Allows Polled or Interrupt-Driven SPI
Interface
♦
Intelligent USB Serial-Interface Engine (SIE)
Automatically Handles USB Flow Control and
Double Buffering
Handles Low-Level USB Signaling Details
Contains Timers for USB Time-Sensitive
Operations So SPI Master Does Not Need to
Time Events
♦
Built-In Endpoint FIFOs
EP0: CONTROL (64 Bytes)
EP1: OUT, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP2: IN, Bulk or Interrupt, 2 x 64 Bytes
(Double-Buffered)
EP3: IN, Bulk or Interrupt (64 Bytes)
♦
Double-Buffered Data Endpoints Increase
Throughput by Allowing the SPI Master to
Transfer Data Concurrently with USB Transfers
Over the Same Endpoint
♦
SETUP Data Has Its Own 8-Byte FIFO, Simplifying
Firmware
♦
Four General-Purpose Inputs and Four General-
Purpose Outputs
♦
Space-Saving LQFP and TQFN Packages
The MAX3420E contains the digital logic and analog
circuitry necessary to implement a full-speed USB
peripheral compliant to USB specification rev 2.0. A
built-in full-speed transceiver features ±15kV ESD pro-
tection and programmable USB connect and discon-
nect. An internal serial-interface engine (SIE) handles
low-level USB protocol details such as error checking
and bus retries. The MAX3420E operates using a regis-
ter set accessed by an SPI™ interface that operates up
to 26MHz. Any SPI master (microprocessor, ASIC, DSP,
etc.) can add USB functionality using the simple 3- or
4-wire SPI interface.
Internal level translators allow the SPI interface to run at
a system voltage between 1.71V and 3.6V. USB timed
operations are done inside the MAX3420E with inter-
rupts provided at completion so an SPI master does not
need timers to meet USB timing requirements. The
MAX3420E includes four general-purpose inputs and
outputs so any microprocessor that uses I/O pins to
implement the SPI interface can reclaim the I/O pins
and gain additional ones.
The MAX3420E operates over the extended -40°C to
+85°C temperature range and is available in a 32-pin
LQFP package (7mm x 7mm) and a space-saving 24-
pin TQFN package (4mm x 4mm).
Applications
Cell Phones
Desktop Routers
PC Peripherals
PLCs
Functional Diagrams
Microprocessors and
Set-Top Boxes
DSPs
PDAs
Custom USB Devices
MP3 Players
Cameras
Instrumentation
Ordering Information
PART
MAX3420EETG+
MAX3420EECJ+
MAX3420EECJ/V+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 TQFN-EP*
32 LQFP
32 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
*
EP = Exposed pad.
/V denotes an automotive qualified part.
Pin Configurations appear at end of data sheet.
Functional Diagrams continued
Inc.
end of data sheet.
SPI is a trademark of Motorola,
at
UCSP is a trademark of Maxim Integrated Products, Inc.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-3781; Rev 3; 12/10
MAX3420E
USB Peripheral Controller
with SPI Interface
Typical Application Circuits
3.3V
REGULATOR
SPI
3, 4
USB
MAX3420E
INT
μP
The MAX3420E connects to any microprocessor using
3 or 4 interface pins (Figure 1). On a simple micro-
processor without SPI hardware, these can be bit-
banged general-purpose I/O pins. Four GPIN and four
GPOUT pins on the MAX3420E more than replace the
µP pins necessary to implement the interface. Although
the MAX3420E SPI hardware includes separate data-in
(MOSI, (master-out, slave-in)) and data-out (MISO,
(master-in, slave-out)) pins, the SPI interface can also
be configured for the MOSI pin to carry bidirectional
data, saving an interface pin. This is referred to as half-
duplex mode.
Figure 1. The MAX3420E Connects to Any Microprocessor
Using 3 or 4 Interface Pins
3.3V
REGULATOR
SPI
3, 4
POWER RAIL
USB
Two MAX3420E features make it easy to connect to
large, fast chips such as ASICs and DSPs (see Figure
2). First, the SPI interface can be clocked up to 26MHz.
Second, a V
L
pin and internal level translators allow
running the system interface at a lower voltage than the
3.3V required for V
CC
.
MAX3420E
INT
ASIC,
DSP,
ETC.
Figure 2. The MAX3420E Connected to a Large Chip
3.3V
REGULATOR
LOCAL
POWER
USB
MAX3420E
I
S
O
L
A
T
O
R
S
MISO
INT
MICRO
ASIC
DSP
SCLK
MOSI
SS
LOCAL
GND
The MAX3420E provides an ideal method for electrically
isolating a USB interface (Figure 3). USB employs flow
control in which the MAX3420E automatically answers
host requests with a NAK handshake, until the micro-
processor completes its data-transfer operations over
the SPI port. This means that the SPI interface can run
at any frequency up to 26MHz. Therefore, the designer
is free to choose the interface operating frequency and
to make opto-isolator choices optimized for cost or per-
formance.
Figure 3. Optical Isolation of USB Using the MAX3420E
2
Maxim Integrated
MAX3420E
USB Peripheral Controller
with SPI Interface
Functional Diagram
V
L
RES
XI
XO
V
CC
INTERNAL
POR
RESET
LOGIC
1.5kΩ
OSC
AND
PLL 4x
POWER
DOWN
D+
D-
ESD
PROTECTION
FULL-SPEED
USB
TRANSCEIVER
USB SIE
(SERIAL-INTERFACE ENGINE)
48MHz
SCLK
MOSI
SPI SLAVE
INTERFACE
ENDPOINT
BUFFERS
SS
VBCOMP
ESD
PROTECTION
VBUS
COMP
1V TO 3V
R
GPIN
VBUS_DET
MISO
INT
VBUS_DET
BUSACT
OPERATE
SOF
3
MAX3420E
0
1
MUX
2
GND
GPX
GPIN3 GPIN2 GPIN1 GPIN0 GPOUT3
GPOUT1
GPOUT0
GPOUT2
Maxim Integrated
3
MAX3420E
USB Peripheral Controller
with SPI Interface
Pin Description
PIN
TQFN-EP
1
2
3
4, 14
5
6
LQFP
1
2
3, 4
5, 6, 18, 19
7
8
NAME
GPOUT0
Output
GPOUT1
V
L
GND
GPOUT2
Output
GPOUT3
Input
Input
INPUT/
OUTPUT
FUNCTION
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on V
L
. The SPI master controls the GPOUT3–GPOUT0
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.
Level-Translator Reference Voltage. Connect V
L
to the system’s 1.71V to 3.6V
logic-level power supply. Bypass V
L
to ground with a 0.1μF capacitor as close
to the V
L
pin as possible.
Ground
General-Purpose Push-Pull Outputs. GPOUT3–GPOUT0 logic levels are
referenced to the voltage on V
L
. The SPI master controls the GPOUT3–GPOUT0
states by writing to bit 3 through bit 0 of the IOPINS (R20) register.
Device Reset. Drive
RES
low to clear all of the internal registers except for
PINCTL (R17), USBCTL (R15), and SPI logic. See the
Device Reset
section for a
description of resets available on the MAX3420E.
Note:
The MAX3420E is
internally reset if either V
CC
of V
L
is not present. The register file is not
accessible under these conditions.
SPI Serial-Clock Input. An external SPI master supplies this clock with
frequencies up to 26MHz. The logic level is referenced to the voltage on V
L
.
Data is clocked into the SPI slave interface on the positive edge of SCLK. Data
is clocked out of the SPI slave interface on the falling edge of SCLK.
SPI Slave-Select Input. The
SS
logic level is referenced to the voltage on V
L
.
When
SS
is driven high, the SPI slave interface is not selected and SCLK
transitions are ignored. An SPI transfer begins with a high-to-low
SS
transition
and ends with a low-to-high
SS
transition.
SPI Serial-Data Output (Master-In, Slave-Out). MISO is a push-pull output. MISO
is tri-stated in half-duplex mode or when
SS
= 1. The MISO logic level is
referenced to the voltage on V
L
.
SPI Serial-Data Input (Master-Out, Slave-In). The logic level on MOSI is
referenced to the voltage on V
L
. MOSI can also be configured as a bidirectional
MOSI/MISO input and output.
General-Purpose Multiplexed Output. The internal MAX3420E signal that
appears on GPX is programmable by writing to the GPXB and GPXA bits of the
PINCTL (R17) register. GPX indicates one of four signals: OPERATE (00,
default), VBUS_DET (01), BUSACT (10), and SOF (11).
Interrupt Output. In edge mode, the logic level on INT is referenced to the
voltage
on VL. In edge mode, INT is a push-pull output with programmable polarity. In
level mode, INT is open-drain and active low. Set the IE bit in the CPUCTL
(R16) register to enable INT.
USB D- Signal. Connect D- to a USB “B” connector through a 33
resistor.
USB D+ Signal. Connect D+ to a USB “B” connector through a 33
resistor. The 1.5k D+ pullup resistor is internal to the device.
±1% series
±1% series
7
10
RES
Input
8
11
SCLK
Input
9
12
SS
Input
10
13
MISO
Output
Input or
Input/
Output
11
14
MOSI
12
15
GPX
Output
13
17
INT
Output
15
16
20
21
D-
D+
Input/
Output
Input/
Output
4
Maxim Integrated
MAX3420E
USB Peripheral Controller
with SPI Interface
Pin Description (continued)
PIN
TQFN-EP
17
LQFP
22, 23
NAME
INPUT/
OUTPUT
Input
FUNCTION
USB Transceiver Power-Supply Input. Connect V
CC
to a positive 3.3V power
supply. Bypass V
CC
to ground with a 1.0μF ceramic capacitor as close to the
V
CC
pin as possible.
V
BUS
Comparator Input. VBCOMP is internally connected to a voltage
comparator to allow the SPI master to detect (through an interrupt or checking a
register bit) the presence or loss of power on V
BUS
. Bypass VBCOMP to ground
with a 1.0μF ceramic capacitor.
Crystal Oscillator Input. Connect XI to one side of a parallel resonant 12MHz
±0.25% crystal and a capacitor to GND. XI can also be driven by an external
clock referenced to V
CC
.
Crystal Oscillator Output. Connect XO to the other side of a parallel resonant
12MHz ±0.25% crystal and a capacitor to GND. Leave XO unconnected if XI is
driven with an external source.
General-Purpose Inputs. GPIN3–GPIN0 are connected to V
L
with internal pullup
resistors. GPIN3–GPIN0 logic levels are referenced to the voltage on V
L
. The
SPI master samples GPIN3–GPIN0 states by reading bit 7 through bit 4 of the
IOPINS (R20) register. Writing to these bits has no effect.
No Internal Connection
Exposed Paddle (TQFN only). Connect EP to GND.
V
CC
18
24
VBCOMP
Input
19
26
XI
Input
20
21
22
23
24
—
—
27
29
30
31
32
9, 16, 25,
28
—
XO
GPIN0
GPIN1
GPIN2
GPIN3
N.C.
EP
Output
Input
—
Input
Register Description
The SPI master controls the MAX3420E by reading and
writing 21 registers (Table 1). For a complete descrip-
tion of register contents, please refer to the “MAX3420E
Programming Guide.” A register access consists of the
SPI master first writing an SPI command byte, followed
by reading or writing the contents of the addressed
register. All SPI transfers are MSB first. The command
byte contains the register address, a direction bit (read
= 0, write = 1), and the ACKSTAT bit (Figure 4). The SPI
master addresses the MAX3420E registers by writing
the binary value of the register number in the Reg4
through Reg0 bits of the command byte. For example,
to access the IOPINS (R20) register, the Reg4 through
b7
Reg4
b6
Reg3
b5
Reg2
b4
Reg1
Reg0 bits would be as follows: Reg4 = 1, Reg3 = 0,
Reg2 = 1, Reg1 = 0, Reg0 = 0. The DIR (direction) bit
determines the direction for the data transfer. DIR = 1
means the data byte(s) will be written to the register,
and DIR = 0 means the data byte(s) will be read from
the register. The ACKSTAT bit sets the ACKSTAT bit in
the EPSTALLS (R9) register. The SPI master sets this
bit to indicate that it has finished servicing a CONTROL
transfer. Since the bit is frequently used, having it in the
SPI command byte improves firmware efficiency. In SPI
full-duplex mode, the MAX3420E clocks out eight USB
status bits as the command byte is clocked in (Figure
5). In half-duplex mode, these status bits are accessed
in the normal way, as register bits.
b3
Reg0
b2
0
b1
DIR
b0
ACKSTAT
Figure 4. SPI Command Byte
b7
SUSPIRQ
b6
URESIRQ
b5
SUDAVIRQ
b4
IN3BAVIRQ
b3
IN2BAVIRQ
b2
OUT1DAVIRQ
b1
OUT0DAVIRQ
b0
IN0BAVIRQ
Figure 5. USB Status Bits Clocked Out as First Byte of Every Transfer (Full-Duplex Mode Only)
Maxim Integrated
5
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