HV2301
Low Charge Injection, 8-Channel, High Voltage,
Enhanced Analog Switch with Bleed Resistors
Features
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HVCMOS technology for high performance
Integrated bleed resistors on the outputs
8 Channels of high voltage analog switch
3.3 or 5.0V CMOS input logic level
20MHz data shift clock frequency
Very low quiescent power dissipation (-10µA)
Low parasitic capacitance
DC to 50MHz analog signal frequency
-60dB typical off-isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
Cascadable serial data register with latches
Flexible operating supply voltages
General Description
The Supertex HV2301 is a low charge injection, 8-channel,
high voltage analog switch integrated circuit (IC) with bleed
resistors. The device can be used in applications requiring high
voltage switching, controlled by low voltage control signals,
such as medical ultrasound imaging, piezoelectric transducer
driver, and printers. The built-in bleed resistors eliminate
voltage built up on capacitive loads such as piezoelectric
transducers. The HV2301 is an enhanced version of the
HV232.
Input data is shifted into an 8-bit shift register that can then
be retained in an 8-bit latch. To reduce any possible clock
feed-through noise, the latch enable bar should be left high
until all bits are clocked in. Data is clocked in during the rising
edge of the clock. Using HVCMOS technology, this device
combines high voltage bilateral DMOS switches and low
power CMOS logic to provide efficient control of high voltage
analog signals.
The device is suitable for various combinations of high
voltage supplies, e.g., V
PP
/V
NN
: +40V/-160V, +100V/-100V,
and +160V/-40V.
Applications
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Medical ultrasound imaging
NDT metal flaw detection
Piezoelectric transducer drivers
Inkjet printer heads
Optical MEMS modules
Block Diagram
LATCHES
D
LE
CL
LEVEL
SHIFTERS
OUTPUT
SWITCHES
SW0
CLK
D
LE
CL
SW1
DIN
8-Bit
Shift
Register
D
LE
CL
SW2
DOUT
D
LE
CL
SW6
D
LE
CL
SW7
VDD GND
LE
CLR
VNN VPP
RGND
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV2301
Ordering Information
Package Options
Device
7.00x7.00mm body
1.60mm height (max)
0.50mm pitch
48-Lead LQFP
.453x.453in body
.180in height (max)
.050in pitch
28-Lead PLCC
HV2301
HV2301FG-G
HV2301PJ-G
-G indicates the part is RoHS compliant (Green)
Absolute Maximum Ratings
Parameter
V
DD
logic supply
V
PP
-V
NN
differential supply
V
PP
positive supply
V
NN
negative supply
Logic input voltage
Analog signal range
Peak analog signal current/channel
Storage temperature
Power dissipation:
48-Lead LQFP
28-Lead PLCC
Value
-0.5V to +7V
220V
-0.5V to V
NN
+200V
+0.5V to -200V
-0.5V to V
DD
+0.3V
V
NN
to V
PP
3.0A
-65°C to 150°C
1.0W
1.2W
Pin Configuration
1
48
48-Lead LQFP (FG)
(top view)
1 28
4
26
28-Lead PLCC (PJ)
(top view)
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Product Marking
Top Marking
Operating Conditions
Sym Parameter
V
DD
V
PP
V
NN
V
IH
V
IL
V
SIG
T
A
Logic power supply voltage
Positive high voltage supply
Negative high voltage supply
High level input voltage
Low-level input voltage
Analog signal voltage
peak-to-peak
Operating free air temperature
Value
3.0V to 5.5V
40V to V
NN
+200V
-40V to -160V
0.9V
DD
to V
DD
0V to 0.1V
DD
V
NN
+10V to V
PP
-10V
0
O
C to 70
O
C
YY = Year Sealed
WW = Week Sealed
L L LL L L L LL
L = Lot Number
Bottom Marking
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
CCCCCCCC
HV2301F G
Y Y WW
AAA
*May be part of top marking
Package may or may not include the following marks: Si or
48-Lead LQFP (FG)
Top Marking
HV2301PJ
YYWW
LLLLLLLLLL
Notes:
1.
Power up/down sequence is arbtrary except GND must be powered-up first and
powered down last.
2.
V
SIG
must be V
NN
≤ V
SIG
≤ V
PP
or floating during power up/down transition.
Rise and fall times of power supplies V
DD
, V
PP
, and V
NN
should not be less than
3.
1.0msec.
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
Package may or may not include the following marks: Si or
28-Lead PLCC (PJ)
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV2301
DC Electrical Characteristics
Sym
Parameter
(Over operating conditions unless otherwise specified )
0
O
C
Min
-
-
Max
30
25
25
18
23
22
20
-
-
5.0
300
500
-
-
-
-
3.0
-
4.0
3.5
3.5
4.5
3.5
3.5
4.0
10
-
-
10
Min
-
-
-
-
-
-
-
-
20
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.45
0.45
-
+25
O
C
Typ
26
22
22
18
20
16
5.0
15
35
1.0
100
100
10
-10
10
-10
3.0
-
-
-
-
-
-
-
-
-
0.70
0.70
-
Max
38
27
27
24
25
25
20
-
50
10
300
500
50
-50
50
-50
2.0
50
5.0
3.5
3.5
5.0
3.5
3.5
4.0
10
-
-
10
+70
O
C
Min
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0.40
0.40
-
Max
48
32
30
27
30
27
20
-
-
15
300
500
-
-
-
-
2.0
-
5.5
3.5
4.0
5.5
3.5
4.0
4.0
10
-
-
10
Units Conditions
I
SIG
= 5.0mA
I
SIG
= 200mA
Ω
I
SIG
= 5.0mA
I
SIG
= 200mA
I
SIG
= 5.0mA
I
SIG
= 200mA
%
Ω
KΩ
μA
mV
mV
μA
μA
μA
μA
A
kHz
V
PP
= +40V
V
NN
= -160V
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
R
ONS
Small signal switch on-resistance
-
-
-
-
ΔR
ONS
R
ONL
R
INT
I
SOL
V
OS
I
PPQ
I
NNQ
I
PPQ
I
NNQ
I
SW
f
SW
Small signal switch on-resistance
matching
Large signal switch on-resistance
Value of output bleed resistance
Switch off leakage per switch
DC offset switch off
DC offset switch on
Quiescent V
PP
supply current
Quiescent V
NN
supply current
Quiescent V
PP
supply current
Quiescent V
NN
supply current
Switch output peak current
Output switching frequency
-
-
-
-
-
-
-
-
-
-
-
-
-
I
SIG
= 5.0mA, V
PP
= +100V,
V
NN
= - 100V
V
SIG
= V
PP
-10V, I
SIG
= 1.0A
Output switch to RGND
I
RINT
= 0.5mA
V
SIG
= V
PP
-10V, V
NN
+10V
No load
All switches off
All switches off
All switches on, I
SW
= 5.0mA
All switches on, I
SW
= 5.0mA
V
SIG
duty cycly < 0.1%
Duty cycle = 50%
V
PP
= +40V
V
NN
= -160V
All output
switches are
turning on and
off at 50kHz
with no load
All output
switches are
turning on and
off at 50kHz
with no load
I
PP
Average V
PP
supply current
-
-
-
mA
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
V
PP
= +40V
V
NN
= -160V
I
NN
Average V
NN
supply curent
-
-
mA
V
PP
= +100V
V
NN
= -100V
V
PP
= +160V
V
NN
= -40V
I
DD
I
DDQ
I
SOR
I
SINK
C
IN
Average V
DD
supply current
Quiescent V
DD
supply current
Data out source current
Data out sink current
Logic input capacitance
-
-
0.45
0.45
-
mA
μA
mA
mA
pF
f
CLK
= 5.0MHz, V
DD
= 5.0V
All logic inputs are static
V
OUT
= V
DD
-0.7V
V
OUT
= 0.7V
---
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV2301
AC Electrical Characteristics
Sym
t
SD
t
WLE
t
DO
t
WCL
t
SU
t
H
f
CLK
t
R
, t
F
t
ON
t
OFF
dv/dt
Parameter
Set up time before LE rises
Time width of LE
(Over recommended operating conditions: V
DD
= 5.0V, t
R
= t
F
≤5ns, 50% duty cycle, C
LOAD
= 20pF unless otherwise specified)
0
O
C
Min
25
56
12
-
-
55
39
16
2
-
-
-
-
-
-
Max
-
-
-
120
58
-
-
-
-
-
20
50
5.0
5.0
20
20
20
-
-
-
300
17
50
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-30
-58
-60
-
5.0
25
-
-
-
-
-
-
-
-
-
Min
25
-
-
-
-
55
47
21
2
-
-
+25
O
C
Typ
-
56
12
95
40
30
30
10
-
-
-
-
-
-
-
-
-
-33
-
-70
-
12
38
-
-
-
-
-
-
820
600
350
Max
-
-
-
140
69
-
-
-
-
8.0
20
50
5.0
5.0
20
20
20
-
-
-
300
17
50
150
150
150
150
150
150
-
-
-
+70
O
C
Min
25
56
12
-
-
55
58
26
2
-
-
-
-
-
-
-
-
-30
-58
-60
-
5.0
25
-
-
-
-
-
-
-
-
-
Max
-
-
-
167
85
-
-
-
-
-
20
50
5.0
5.0
20
20
20
-
-
-
300
17
50
-
-
-
-
-
-
-
-
-
Units
ns
ns
Conditions
---
V
DD
= 3.0V
V
DD
= 5.0V
V
DD
= 3.0V
V
DD
= 5.0V
---
V
DD
= 3.0V
V
DD
= 5.0V
V
DD
= 3.0 or 5.0V
V
DD
= 3.0V
V
DD
= 5.0V
---
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
SIG
= V
PP
-10V, R
LOAD
= 10kΩ
V
PP
= +40V, V
NN
= -160V
V
PP
= +100V, V
NN
= -100V
V
PP
= +160V, V
NN
= -40V
f = 5.0MHz, 1kΩ/15pF load
f = 5.0MHz, 50Ω load
f = 5.0MHz, 50Ω load
300ns pulse width,
2.0% duty cycle
0V, f = 1.0MHz
0V, f = 1.0MHz
V
PP
= +40V, V
NN
= -160V,
R
LOAD
= 50Ω
Clock delay time to data out
Time width of CL
Set up time data to clock
Hold time data from clock
Clock frequency
Clock rise and fall times
Turn on time
Turn off time
ns
ns
ns
ns
MHz
ns
μs
μs
Maximun V
SIG
slew rate
-
-
V/ns
K
O
K
CR
I
ID
Off isolation
Switch crosstalk
Output switch isolation diode
current
On capacitance SW to GND
-30
-58
-60
-
5.0
25
-
-
dB
dB
mA
pF
pF
C
SG(OFF)
Off capacitance SW to GND
C
SG(ON)
+V
SPK
-V
SPK
+V
SPK
-V
SPK
+V
SPK
-V
SPK
Output voltage spike
-
-
-
-
-
mV
V
PP
= +100V, V
NN
= -100V,
R
LOAD
= 50Ω
V
PP
= +160V, V
NN
= -40V,
R
LOAD
= 50Ω
V
PP
= +40V, V
NN
= -160V,
V
SIG
= 0V
QC
Charge injection
-
-
pC
V
PP
= +100V, V
NN
= -100V,
V
SIG
= 0V
V
PP
= +160V, V
NN
= -40V,
V
SIG
= 0V
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV2301
Truth Table
D0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D1
D2
D3
D4
D5
D6
D7
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CLR
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Hold Previous State
All Switches Off
SW0
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
Off
On
SW1
SW2
SW3
SW4
SW5
SW6
SW7
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. D
OUT
is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
Typical Waveforms
DATA
IN
D
N+1
D
N
D
N -1
5 0%
50%
LE
50%
50%
t
WLE
t
SD
CLOCK
t
SU
50%
t
DO
50%
t
OFF
50%
t
h
DATA
O UT
t
ON
VOUT
(Typ)
OFF
ON
CLR
5 0%
5 0%
90%
1 0%
t
WCL
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
NXP MCU
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