CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1.
θ
JA
is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
HI5760
T
A
= -40
o
C TO 85
o
C
PARAMETER
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
OS
Offset Drift Coefficient
Full Scale Gain Error, FSE
TEST CONDITIONS
MIN
TYP
MAX
UNITS
10
“Best Fit” Straight Line (Note 7)
(Note 7)
(Note 7)
(Note 7)
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
-1
-0.5
-0.025
-
-10
-10
-
-
2
(Note 3)
-0.3
-
±0.5
±0.25
-
+1
+0.5
+0.025
Bits
LSB
LSB
% FSR
ppm
FSR/
o
C
% FSR
% FSR
ppm
FSR/
o
C
ppm
FSR/
o
C
mA
V
0.1
±2
±1
±50
±100
-
-
-
+10
+10
-
-
20
1.25
Full Scale Gain Drift
With External Reference (Note 7)
With Internal Reference (Note 7)
Full Scale Output Current, I
FS
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
CLK
Output Settling Time, (t
SETT
)
(Note 3)
0.2% (±1 LSB, equivalent to 9 Bits) (Note 7)
0.1% (±1/2 LSB, equivalent to 10 Bits) (Note 7)
Singlet Glitch Area (Peak Glitch)
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
IOUTFS = 20mA
IOUTFS = 2mA
R
L
= 25Ω (Note 7)
Full Scale Step
Full Scale Step
125
-
-
-
-
-
-
-
-
-
20
35
5
1.0
1.5
10
50
30
-
-
-
-
-
-
-
-
-
MHz
ns
ns
pV•s
ns
ns
pF
pA/√Hz
pA/√Hz
3
HI5760
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
HI5760
T
A
= -40
o
C TO 85
o
C
PARAMETER
AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 4MHz Span (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 2MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 2MHz Span (Notes 4, 7)
Total Harmonic Distortion (THD) to
Nyquist
f
CLK
= 100MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 7)
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 125MSPS, f
OUT
= 32.9MHz, 62.5MHz Span (Notes 4, 7)
f
CLK
= 125MSPS, f
OUT
= 10.1MHz, 62.5MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 40.4MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 20.2MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 5.04MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 100MSPS, f
OUT
= 2.51MHz, 50MHz Span (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 2.51MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 25MHz Span (Notes 4, 7)
AC CHARACTERISTICS - HI5760/6IB, HI5760/6IA - 60MHz
Spurious Free Dynamic Range,
SFDR Within a Window
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 10MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 2MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 2MHz Span (Notes 4, 7)
Total Harmonic Distortion (THD) to
Nyquist
Spurious Free Dynamic Range,
SFDR to Nyquist
f
CLK
= 50MSPS, f
OUT
= 2.00MHz (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 20.2MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 60MSPS, f
OUT
= 10.1MHz, 30MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 20.2MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 2.51MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 50MSPS, f
OUT
= 1.00MHz, 25MHz Span (Notes 4, 7)
f
CLK
= 25MSPS, f
OUT
= 5.02MHz, 25MHz Span (Notes 4, 7)
VOLTAGE REFERENCE
Internal Reference Voltage, V
FSADJ
Internal Reference Voltage Drift
Internal Reference Output Current
Sink/Source Capability
Reference Input Impedance
Reference Input Multiplying Bandwidth (Note 7)
Pin 18 Voltage with Internal Reference
1.04
-
-
-
-
1.16
±60
0.1
1
1.4
1.28
-
-
-
-
V
ppm
/
o
C
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
75
76
75
76
78
71
71
76
54
64
52
60
68
74
63
55
68
73
73
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
-
-
-
-
-
-
-
-
-
-
-
-
75
76
78
71
76
56
63
55
68
73
73
71
-
-
-
-
-
-
-
-
-
-
-
-
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
µA
MΩ
MHz
4
HI5760
Electrical Specifications
AV
DD
= DV
DD
= +5V, V
REF
= Internal 1.2V, IOUTFS = 20mA, T
A
= 25
o
C for All Typical Values
(Continued)
HI5760
T
A
= -40
o
C TO 85
o
C
PARAMETER
DIGITAL INPUTS
D9-D0, CLK
(Note 3)
(Note 3)
(Note 3)
(Note 3)
3.5
2.1
-
-
-10
-10
-
5
3
0
0
-
-
5
-
-
1.3
0.9
+10
+10
-
V
V
V
V
µA
µA
pF
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Logic High Voltage with
5V Supply, V
IH
Input Logic High Voltage with
3V Supply, V
IH
Input Logic Low Voltage with
5V Supply, V
IL
Input Logic Low Voltage with
3V Supply, V
IL
Input Logic Current, I
IH
Input Logic Current, I
IL
Digital Input Capacitance, C
IN
TIMING CHARACTERISTICS
Data Setup Time, t
SU
Data Hold Time, t
HLD
Propagation Delay Time, t
PD
CLK Pulse Width, t
PW1
, t
PW2
See Figure 41 (Note 3)
See Figure 41 (Note 3)
See Figure 41
See Figure 41 (Note 3)
3
3
-
4
-
-
1
-
-
-
-
-
ns
ns
ns
ns
POWER SUPPLY CHARACTERISTICS
AV
DD
Power Supply
DV
DD
Power Supply
Analog Supply Current (I
AVDD
)
(Note 8)
(Note 8)
(5V or 3V, IOUTFS = 20mA)
(5V or 3V, IOUTFS = 2mA)
Digital Supply Current (I
DVDD
)
(5V, IOUTFS = Don’t Care) (Note 5)
(3V, IOUTFS = Don’t Care) (Note 5)
Supply Current (I
AVDD
) Sleep Mode
Power Dissipation
(5V or 3V, IOUTFS = Don’t Care)
(5V, IOUTFS = 20mA) (Note 6)
(5V, IOUTFS = 2mA) (Note 6)
(5V, IOUTFS = 20mA) (Note 9)
(3.3V, IOUTFS = 20mA) (Note 9)
(3V, IOUTFS = 20mA) (Note 6)
(3V, IOUTFS = 20mA) (Note 9)
(3V, IOUTFS = 2mA) (Note 6)
Power Supply Rejection
NOTES:
2. Gain Error measured as the error in the ratio between the full scale output current and the current through R
SET
(typically 625µA). Ideally the
ratio should be 31.969.
3. Parameter guaranteed by design or characterization and not production tested.
4. Spectral measurements made with differential coupled transformer.
5. Measured with the clock at 50MSPS and the output frequency at 1MHz.
6. Measured with the clock at 100MSPS and the output frequency at 40MHz.
7. See ‘Definition of Specifications’.
8. It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V. DV
DD
and AV
DD
do not have to be equal.
9. Measured with the clock at 60MSPS and the output frequency at 10MHz.
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