FemtoClock
®
NG Universal Frequency
Translator with Phase Build-Out
IDT8T49N205I
PRELIMINARY PRODUCT BRIEF
This is a product brief and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found
on the last page.
General Description
The IDT8T49N205I is a highly flexible FemtoClock
®
NG general
purpose, low phase noise Frequency Translator / Synthesizer with
Phase Build-Out (PBO) suitable for networking and communications
applications. It is able to generate any output frequency in the
0.98MHz - 312.5MHz range and most output frequencies in the
312.5MHz - 1,300MHz range (see Table 3 for details). A wide range
of input reference clocks and a range of low-cost fundamental mode
crystal frequencies may be used as the source for the output
frequency.
The IDT8T49N205I has three operating modes to support a very
broad spectrum of applications:
1
Frequency Synthesizer
Features
•
•
•
•
•
•
•
Fourth Generation FemtoClock
®
NG technology
Universal Frequency Translator/Frequency Synthesizer
•
•
•
•
Zero ppm frequency translation
Both outputs may be set to use 2.5V or 3.3V output levels
Programmable output frequency: 0.98MHz up to 1,300MHz
Two outputs, individually programmable as LVPECL or LVDS
Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, HCSL
Input frequency range: 8kHz - 710MHz
Phase Build-Out minimizes output phase change on switchover
Crystal input frequency range: 16MHz - 40MHz
Two factory-set register configurations for power-up default state
•
•
Synthesizes output frequencies from a 16MHz - 40MHz
fundamental mode crystal.
Fractional feedback division is used, so there are no
requirements for any specific crystal frequency to produce the
desired output frequency with a high degree of accuracy.
Applications: PCI Express, Computing, General Purpose
Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation, so it will not attenuate much jitter on the input
reference.
Applications: Networking & Communications.
Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external crystal to provide
significant jitter attenuation.
2) High-Bandwidth Frequency Translator
•
•
•
•
•
•
•
•
•
Power-up default configuration pin or register selectable
Configurations customized via One-Time Programmable ROM
Settings may be overwritten after power-up via I
2
C
I
2
C Serial interface for register programming
RMS phase jitter at 155.52MHz, using a 40MHz crystal
(12kHz - 20MHz): 463fs (typical), Low Bandwidth Mode (FracN)
Output supply voltage modes:
V
CC
/V
CCA
/V
CCO
3.3V/3.3V/3.3V
3.3V/3.3V/2.5V (LVPECL only)
2.5V/2.5V/2.5V
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) packaging
3) Low-Bandwidth Frequency Translator
•
•
•
•
•
This device provides two factory-programmed default power-up
configurations burned into One-Time Programmable (OTP) memory.
The configuration to be used is selected by the CONFIG pin. The two
configurations are specified by the customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices. The two configurations may be completely independent of
one another.
One usage example might be to install the device on a line card with
two optional daughter cards: an OC-12 option requiring a 622.08MHz
LVDS clock translated from a 19.44MHz input and a Gigabit Ethernet
option requiring a 125MHz LVPECL clock translated from the same
19.44MHz input reference.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I
2
C interface and the
device can be completely reconfigured. However, these settings
would have to be re-written next time the device powers-up.
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT8T49N205NLGI REVISION A OCTOBER 11, 2012
1
©2012 Integrated Device Technology, Inc.
IDT8T49N205I Preliminary Product Brief
FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT
Complete Block Diagram
IDT8T49N205NLGI REVISION A
OCTOBER 11, 2012
2
©2012 Integrated Device Technology, Inc.
IDT8T49N205I Preliminary Product Brief
FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT
Functional Description
The IDT8T49N205I is designed to provide two copies of almost any
desired output frequency within its operating range (0.98 - 1300MHz)
from any input source in the operating range (8kHz - 710MHz). It is
capable of synthesizing frequencies from a crystal or crystal
oscillator source. The output frequency is generated regardless of
the relationship to the input frequency. The output frequency will be
exactly the required frequency in most cases. In most others, it will
only differ from the desired frequency by a few ppb. IDT configuration
software will indicate the frequency error, if any. The IDT8T49N205I
can translate the desired output frequency from one of two input
clocks. Again, no relationship is required between the input and
output frequencies in order to translate to the output clock rate. In this
frequency translation mode, a low-bandwidth, jitter attenuation option
is available that makes use of an external fixed-frequency crystal or
crystal oscillator to translate from a noisy input source. If the input
clock is known to be fairly clean or if some modulation on the input
needs to be tracked, then the high-bandwidth frequency translation
mode can be used, without the need for the external crystal.
The input clock references and crystal input are monitored
continuously and appropriate alarm outputs are raised both as
register bits and hard-wired pins in the event of any
out-of-specification conditions arising. Clock switching is supported
in manual, revertive & non-revertive modes.
The IDT8T49N205I has two factory-programmed configurations that
may be chosen from as the default operating state after reset. This is
intended to allow the same device to be used in two different
applications without any need for access to the I
2
C registers. These
defaults may be over-written by I
2
C register access at any time, but
those over-written settings will be lost on power-down. Please
contact IDT if a specific set of power-up default settings is desired.
It is expected that the IDT8T49N205I will be used almost exclusively
in a mode where the selected configuration will be used from device
power-up without any changes during operation. For example, the
device may be designed into a communications line card that
supports different I/O modules such as a standard OC-12 module
running at 622.08MHz or a (255/237) FEC rate OC-12 module
running at 669.32MHz. The different I/O modules would result in a
different level on the CONFIG pin which would select different divider
ratios within the IDT8T49N205I for the two different card
configurations. Access via I
2
C would not be necessary for operation
using either of the internal configurations.
Operating Modes
The IDT8T49N205I has three operating modes. There are two
frequency translator modes - low bandwidth and high bandwidth and
a frequency synthesizer mode. The device will operate in the same
mode regardless of which configuration is active.
Output Dividers & Supported Output Frequencies
In all 3 operating modes, the output stage behaves the same way, but
different operating frequencies can be specified in the two
configurations.
The internal VCO is capable of operating in a range anywhere from
1.995GHz - 2.6GHz. It is necessary to choose an integer multiplier of
the desired output frequency that results in a VCO operating
frequency within that range. The output divider stage N[10:0] is
limited to selection of integers from 2 to 2046. Please refer to Table 3
for the values of N applicable to the desired output frequency.
Table 3. Output Divider Settings & Frequency Ranges
Register
Setting
Nn[10:0]
0000000000x
00000000010
00000000011
00000000100
00000000101
0000000011x
0000000100x
0000000101x
...
1111111111x
Frequency
Divider
N
2
2
3
4
5
6
8
10
Even N
2046
Minimum
f
OUT
(MHz)
997.5
997.5
665
498.75
399
332.5
249.4
199.5
1995 / N
0.98
Maximum
f
OUT
(MHz)
1300
1300
866.7
650
520
433.3
325
260
2600 / N
1.27
Configuration Selection
The IDT8T49N205I comes with two factory-programmed default
configurations. When the device comes out of power-up reset the
selected configuration is loaded into operating registers. The
IDT8T49N205I uses the state of the CONFIG pin or CONFIG register
bit (controlled by the CFG_PIN_REG bit) to determine which
configuration is active. When the output frequency is changed either
via the CONFIG pin or via internal registers, the output behavior may
not be predictable during the register writing and output settling
periods. Devices sensitive to glitches or runt pulses may have to be
reset once reconfiguration is complete.
Once the device is out of reset, the contents of the operating registers
can be modified by write access from the I
2
C serial port. Users that
have a custom configuration programmed may not require I
2
C
access.
IDT8T49N205NLGI REVISION A
OCTOBER 11, 2012
3
©2012 Integrated Device Technology, Inc.
IDT8T49N205I Preliminary Product Brief
FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT
Frequency Synthesizer Mode
This mode of operation allows an arbitrary output frequency to be
generated from a fundamental mode crystal input. For improved
phase noise performance, the crystal input frequency may be
doubled. As can be seen from the block diagram in
Figure 1,
only the
upper feedback loop is used in this mode of operation. It is
recommended that CLK0 and CLK1 be left unused in this mode of
operation.
The upper feedback loop supports a delta-sigma fractional feedback
divider. This allows the VCO operating frequency to be a non-integer
multiple of the crystal frequency. By using an integer multiple only,
lower phase noise jitter on the output can be achieved, however the
use of the delta-sigma divider logic will provide excellent
performance on the output if a fractional divisor is used.
The input reference frequency range is now extended up to 710MHz.
A pre-divider stage P is needed to keep the operating frequencies at
the phase detector less than 100MHz.
Low-Bandwidth Frequency Translator Mode
As can be seen from the block diagram in Figure 3, this mode
involves two PLL loops. The lower loop with the large integer dividers
is the low bandwidth loop and it sets the output-to-input frequency
translation ratio.This loop drives the upper DCXO loop (digitally
controlled crystal oscillator) via an analog-digital converter.
Figure 3. Low Bandwidth Frequency Translator Mode
Block Diagram
The pre-divider stage is used to scale down the input frequency by
an integer value to achieve a frequency in this range. By dividing
down the fed-back VCO operating frequency by the integer divider
M1[16:0] to as close as possible to the same frequency, exact output
frequency translations can be achieved. For improved phase noise
performance, the crystal input frequency may be doubled. The phase
detector of the lower loop is designed to work with frequencies in the
8kHz - 16kHz range. For improved phase noise performance, the
crystal input frequency may be doubled.
Figure 1. Frequency Synthesizer Mode Block Diagram
High-Bandwidth Frequency Translator Mode
This mode of operation is used to translate one of two input clocks of
the same nominal frequency into an output frequency with little jitter
attenuation. As can be seen from the block diagram in Figure 2,
similarly to the Frequency Synthesizer mode, only the upper
feedback loop is used.
Alarm Conditions & Status Bits
The IDT8T49N205I monitors a number of conditions and reports their
status via both output pins and register bits.
CLK_ACTIVE - indicates which input clock reference is being used to
derive the output frequency.
LOCK_IND - This status is asserted on the pin & register bit when the
PLL is locked to the appropriate input reference for the chosen mode
of operation. The status bit will not assert until frequency lock has
been achieved, but will de-assert once lock is lost.
Figure 2. High Bandwidth Frequency Translator Mode
Block Diagram
IDT8T49N205NLGI REVISION A
OCTOBER 11, 2012
4
©2012 Integrated Device Technology, Inc.
IDT8T49N205I Preliminary Product Brief
FEMTOCLOCK® NG UNIVERSAL FREQUENCY TRANSLATOR WITH PHASE BUILD-OUT
XTALBAD - indicates if valid edges are being received on the crystal
input.
CLK0BAD - indicates if valid edges are being received on the CLK0
reference input.
CLK1BAD - indicates if valid edges are being received on the CLK1
reference input. Behavior is as indicated for the CLK0BAD alarm, but
with the CLK1 input being monitored and the CLK1BAD output pin &
register bits being affected.
HOLDOVER - indicates that the device is not locked to a valid input
reference clock. This can occur in Manual switchover mode if the
selected reference input has gone bad, even if the other reference
input is still good. In automatic mode, this will only assert if both input
references are bad.
automatically switch to the other input reference as long as there is a
valid clock there. If there is not a valid clock on either input reference,
the IDT8T49N205I will go into holdover or free-run state. In either
case, the HOLDOVER alarm will be raised.
The device will recover from holdover / free-run state once a valid
clock is re-established on either reference input. If clocks are valid on
both input references, the device will choose the reference indicated
by the CLK_SEL register bit.
If running from the non-preferred input reference and a valid clock
returns, there is a difference in behavior between Revertive and
Non-revertive modes. In Revertive mode, the device will switch back
to the reference indicated by the CLK_SEL register bit even if there
is still a valid clock on the non-preferred reference input. In
Non-revertive mode, the IDT8T49N205I will not switch back as long
as the non-preferred input reference still has a valid clock on it.
Input Reference Selection and Switching
When operating in Frequency Synthesizer mode, the CLK0 and
CLK1 inputs are not used and the contents of this section do not
apply. Except as noted below, when operating in either High or Low
Bandwidth Frequency Translator mode, the contents of this section
apply equally when in either of those modes.
Both input references CLK0 and CLK1 must be the same nominal
frequency. These may be driven by any type of clock source,
including crystal oscillator modules. A difference in frequency may
cause the PLL to lose lock when switching between input references.
Please contact IDT for the exact limits for your situation.
Switchover Behavior of the PLL
Even though the two input references have the same nominal
frequency, there may be minor differences in frequency and
potentially large differences in phase between them. The
IDT8T49N205I has two options: Phase Build-Out or Phase-Slope
Limiting to determine how it will adjust its output to the new input
reference when operating in Low-Bandwidth mode. Only
Phase-Slope limiting is available in High-Bandwidth mode.
In Phase Slope Limiting operation, the IDT8T49N205I will adjust the
output phase at a fixed maximum rate until the output phase and
frequency are now aligned to the new input reference. Phase will
always be adjusted so that no unacceptably short clock periods are
generated on the output of the IDT8T49N205I. Please contact IDT if
more information on the maximum phase slope adjustment rate is
needed.
In Phase Build-Out operation, the device will absorb most of the
phase difference between the two inputs (or between the input and
current VCO setting if recovering from holdover). Any phase
difference that is not absorbed will be reflected on the output at the
same maximum rate as in Phase Slope Limiting operation.
Manual Switching Mode
When set to Manual via Pin, then the IDT8T49N205I will use the
CLK_SEL input pin to determine which input to use as a reference.
Similarly, if set to Manual via Register, then the device will use the
CLK_SEL register bit to determine the input reference. In either case,
the PLL will lock to the selected reference if there is a valid clock
present on that input.
If there is not a valid clock present on the selected input, the
IDT8T49N205I will go into holdover or free-run state. In either case,
the HOLDOVER alarm will be raised. This will occur even if there is
a valid clock on the non-selected reference input. The device will
recover from holdover / free-run state once a valid clock is
re-established on the selected reference input.
The IDT8T49N205I will only switch input references on command
from the user. The user must either change the CLK_SEL register bit
(if in Manual via Register) or CLK_SEL input pin (if in Manual via Pin).
Holdover / Free-run Behavior
When both input references have failed (Automatic mode) or the
selected input has failed (Manual mode), the IDT8T49N205I will
enter holdover or free-run state.
If the device is programmed to perform Manual switching, once the
selected input reference recovers, the IDT8T49N205I will switch back
to that input reference. If programmed for either Automatic mode, the
device will switch back to whichever input reference has a valid clock
first.
The switchover that results from returning from holdover or free-run
is handled in the same way as a switch between two valid input
references as described in the previous section.
Automatic Switching Mode
When set to either of the automatic selection modes (Revertive or
Non-Revertive), the IDT8T49N205I determines which input
reference it prefers / starts from by the state of the CLK_SEL register
bit only. The CLK_SEL input pin is not used in either Automatic
switching mode.
Once the IDT8T49N205I has achieved a stable lock, it will remain
locked to the preferred input reference as long as there is a valid clock
on it. If at some point, that clock fails, then the device will
IDT8T49N205NLGI REVISION A
OCTOBER 11, 2012
5
©2012 Integrated Device Technology, Inc.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
